[PATCH -next 1/3] clk: sprd: composite: Fix unsigned comparison with less than zero

[PATCH -next 1/3] clk: sprd: composite: Fix unsigned comparison with less than zero

[Yang Li]

The return value of the sprd_div_helper_round_rate() is long.
However, the return value is being assigned to an unsigned
long variable 'rate', so making 'rate' to long.

silence the warning:
./drivers/clk/sprd/composite.c:20:5-9: WARNING: Unsigned expression
compared with zero: rate < 0

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
 drivers/clk/sprd/composite.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sprd/composite.c b/drivers/clk/sprd/composite.c
index d3a852720c07..e4d22d8f113f 100644
--- a/drivers/clk/sprd/composite.c
+++ b/drivers/clk/sprd/composite.c
@@ -13,7 +13,7 @@ static int sprd_comp_determine_rate(struct clk_hw *hw,
 				    struct clk_rate_request *req)
 {
 	struct sprd_comp *cc = hw_to_sprd_comp(hw);
-	unsigned long rate;
+	long rate;
 
 	rate = sprd_div_helper_round_rate(&cc->common, &cc->div,
 					  req->rate, &req->best_parent_rate);
-- 
2.20.1.7.g153144c

[PATCH -next 2/3] clk: stm32: core: Fix unsigned comparison with less than zero

[Yang Li]

The return value of the divider_ro_round_rate() is long.
However, the return value is being assigned to an unsigned
long variable 'rate', so making 'rate' to long.

silence the warnings:
./drivers/clk/stm32/clk-stm32-core.c:451:6-10: WARNING: Unsigned expression compared with zero: rate < 0
./drivers/clk/stm32/clk-stm32-core.c:461:5-9: WARNING: Unsigned expression compared with zero: rate < 0

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
 drivers/clk/stm32/clk-stm32-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
index d5aa09e9fce4..067b918a8894 100644
--- a/drivers/clk/stm32/clk-stm32-core.c
+++ b/drivers/clk/stm32/clk-stm32-core.c
@@ -431,7 +431,7 @@ static int clk_stm32_composite_determine_rate(struct clk_hw *hw,
 {
 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
 	const struct stm32_div_cfg *divider;
-	unsigned long rate;
+	long rate;
 
 	if (composite->div_id == NO_STM32_DIV)
 		return 0;
-- 
2.20.1.7.g153144c

[PATCH -next 3/3] clk: tegra: Fix unsigned comparison with less than zero

[Yang Li]

The return value of the round_rate() is long. However, the
return value is being assigned to an unsigned long variable
'rate', so making 'rate' to long.

silence the warnings:
./drivers/clk/tegra/clk-periph.c:59:5-9: WARNING: Unsigned expression compared with zero: rate < 0
./drivers/clk/tegra/clk-super.c:156:5-9: WARNING: Unsigned expression compared with zero: rate < 0

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
 drivers/clk/tegra/clk-periph.c | 2 +-
 drivers/clk/tegra/clk-super.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 0626650a7011..9eaac49facd4 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -51,7 +51,7 @@ static int clk_periph_determine_rate(struct clk_hw *hw,
 	struct tegra_clk_periph *periph = to_clk_periph(hw);
 	const struct clk_ops *div_ops = periph->div_ops;
 	struct clk_hw *div_hw = &periph->divider.hw;
-	unsigned long rate;
+	long rate;
 
 	__clk_hw_set_clk(div_hw, hw);
 
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 7ec47942720c..7a121de526c0 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -147,7 +147,7 @@ static int clk_super_determine_rate(struct clk_hw *hw,
 {
 	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
 	struct clk_hw *div_hw = &super->frac_div.hw;
-	unsigned long rate;
+	long rate;
 
 	__clk_hw_set_clk(div_hw, hw);
 
-- 
2.20.1.7.g153144c

Re: [PATCH -next 2/3] clk: stm32: core: Fix unsigned comparison with less than zero

[Stephen Boyd]

Quoting Yang Li (2023-06-13 18:29:12)
> The return value of the divider_ro_round_rate() is long.
> However, the return value is being assigned to an unsigned
> long variable 'rate', so making 'rate' to long.
> 
> silence the warnings:
> ./drivers/clk/stm32/clk-stm32-core.c:451:6-10: WARNING: Unsigned expression compared with zero: rate < 0
> ./drivers/clk/stm32/clk-stm32-core.c:461:5-9: WARNING: Unsigned expression compared with zero: rate < 0
> 
> Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
> ---
>  drivers/clk/stm32/clk-stm32-core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c
> index d5aa09e9fce4..067b918a8894 100644
> --- a/drivers/clk/stm32/clk-stm32-core.c
> +++ b/drivers/clk/stm32/clk-stm32-core.c
> @@ -431,7 +431,7 @@ static int clk_stm32_composite_determine_rate(struct clk_hw *hw,
>  {
>         struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
>         const struct stm32_div_cfg *divider;
> -       unsigned long rate;
> +       long rate;
>  

Instead of this can you convert this code to use
divider_ro_determine_rate() and divider_determine_rate()?

Re: [PATCH -next 3/3] clk: tegra: Fix unsigned comparison with less than zero

[Stephen Boyd]

Quoting Yang Li (2023-06-13 18:29:13)
> The return value of the round_rate() is long. However, the
> return value is being assigned to an unsigned long variable
> 'rate', so making 'rate' to long.
> 
> silence the warnings:
> ./drivers/clk/tegra/clk-periph.c:59:5-9: WARNING: Unsigned expression compared with zero: rate < 0
> ./drivers/clk/tegra/clk-super.c:156:5-9: WARNING: Unsigned expression compared with zero: rate < 0
> 
> Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
> ---
>  drivers/clk/tegra/clk-periph.c | 2 +-
>  drivers/clk/tegra/clk-super.c  | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Instead of this can you implement determine_rate() for div_ops?