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X-CSE-ConnectionGUID: sWQ/eF9UQVC2aTSYGz1XLw== X-CSE-MsgGUID: MrFl5L8ETM60gwscNFX07Q== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="38942712" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="38942712" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 10:47:24 -0700 X-CSE-ConnectionGUID: bTHO+195SemDrWLFww8K9A== X-CSE-MsgGUID: D2O/ikGbRaqmcNTYRpFIAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="80889213" Received: from uaeoff-desk2.amr.corp.intel.com (HELO [10.124.223.14]) ([10.124.223.14]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 10:47:21 -0700 Message-ID: Date: Wed, 9 Oct 2024 10:47:19 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2] x86/apic: Stop the TSC Deadline timer during lapic timer shutdown To: Zhang Rui , tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, rafael.j.wysocki@intel.com, x86@kernel.org, linux-pm@vger.kernel.org Cc: hpa@zytor.com, peterz@infradead.org, thorsten.blum@toblux.com, yuntao.wang@linux.dev, tony.luck@intel.com, len.brown@intel.com, srinivas.pandruvada@intel.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20241009072001.509508-1-rui.zhang@intel.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/9/24 00:20, Zhang Rui wrote: > diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c > index 6513c53c9459..d1006531729a 100644 > --- a/arch/x86/kernel/apic/apic.c > +++ b/arch/x86/kernel/apic/apic.c > @@ -441,6 +441,10 @@ static int lapic_timer_shutdown(struct clock_event_device *evt) > v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); > apic_write(APIC_LVTT, v); > apic_write(APIC_TMICT, 0); > + > + if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) > + wrmsrl(MSR_IA32_TSC_DEADLINE, 0); One last thing, and this is a super nit. We presumably have the actual APIC_LVTT value (v) sitting in a register already. Is there any difference logically between a X86_FEATURE_TSC_DEADLINE_TIMER check and an APIC_LVTT check for APIC_LVT_TIMER_TSCDEADLINE? I suspect this will generate more compact code: if (v & APIC_LVT_TIMER_TSCDEADLINE) wrmsrl(MSR_IA32_TSC_DEADLINE, 0); Does it have any downsides? Oh, and how hot is this path? Is this wrmsr() going to matter? I presume it's pretty cheap because it's one of the special architecturally non-serializing WRMSRs.