Re: [RFC PATCH v2 5/5] docs: ABI: Add sysfs documentation interface of hardware prefetch driver

[Dave Hansen <dave.hansen@intel.com>]

On 11/9/21 1:41 AM, tarumizu.kohei@fujitsu.com wrote:
>> I guess that's OK, but will folks ever want to do "L2
>> Hardware Prefetcher Disable", but not "L2 Adjacent Cache Line Prefetcher
>> Disable"?
> There are people who actually tested the performance improvement[1].
> 
> [1]https://github.com/xmrig/xmrig/issues/1433#issuecomment-572126184
> 
> In this report, write 5 to MSR 0x1a4 (i.e. "L2 Hardware Prefetcher
> Disable", but not "L2 Adjacent Cache Line Prefetcher Disable")
> on i7-5930K for best performance. If such tuning is possible, it may
> be useful for some people.
> 
> We describe how to deal these parameters in our sysfs interface at
> "[RFC & Future plan]" section in the cover letter(0/5), but we can't
> come up with any good ideas.
> 
> We thought that the sysfs interface should be generic and common,
> and avoid showing architecture-dependent specifications.
> 
> We have considered the Proposal B that multiple hardware prefetch
> types in one enable attribute file at above section. However, in
> order to use it, we have to know the register specification, so we
> think it is not appropriate.
> 
> Do you have any idea how to represent architecture-dependent
> specifications in sysfs interface?

First, I'd give them real names.

Second, I'd link them to the level or levels of the cache that they effect.

Third, I'd make sure that it is clear what caches it affects.

We have a representation of the caches in:

	/sys/devices/system/cpu/cpu*/cache

It would be a shame to ignore those.