[PATCH v3 0/2] arm64: dts: qcom: Add DT support for secondary USB on QCS615

[PATCH v3 0/2] arm64: dts: qcom: Add DT support for secondary USB on QCS615

[Song Xue]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

These series aim at enabling secondary USB on QCS615. The secondary
controller is High Speed capable and has a QUSB2 Phy.

Base DT Support has been added and is enabled on Ride Platform. The
secondary controller is enabled in host mode.

Signed-off-by: Song Xue <quic_songxue@quicinc.com>
---
Dependencies:
Link to bindings and driver changes:
https://lore.kernel.org/all/20241017130701.3301785-1-quic_kriskura@quicinc.com/

PMIC DT:
https://lore.kernel.org/all/20241202-adds-spmi-pmic-peripherals-for-qcs615-v6-0-bdd306b4940d@quicinc.com/

---
Changes in v3:
- Make a vertical list for clocks property of usb_hsphy_2 node in SOC DT.
- Move GPIO10 node of PM8150 to fixed regulator node to enable high level. 
- Use subject prefixes matching the subsystem for SOC DT and Board DT.
- Link to v2: https://lore.kernel.org/r/20241211-add_usb_host_mode_for_qcs615-v2-0-2c4abdf67635@quicinc.com

Changes in v2:
- Modified "0" dec to "0x0" hex in reg property. 
- Link to v1: https://lore.kernel.org/r/20241211-add_usb_host_mode_for_qcs615-v1-0-edce37204a85@quicinc.com

---
Krishna Kurapati (2):
      arm64: dts: qcom: qcs615: Add support for secondary USB node on QCS615
      arm64: dts: qcom: qcs615-ride: Enable secondary USB controller on QCS615 Ride

 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 36 +++++++++++++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi     | 78 ++++++++++++++++++++++++++++++++
 2 files changed, 114 insertions(+)
---
base-commit: f2b086fc9f039773445d2606dc65dc091ec1830f
change-id: 20241211-add_usb_host_mode_for_qcs615-61feb12fabd0

Best regards,
-- 
Song Xue <quic_songxue@quicinc.com>

[PATCH v3 1/2] arm64: dts: qcom: qcs615: Add support for secondary USB node on QCS615

[Song Xue]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Add support for secondary USB controller and its high-speed phy
on QCS615.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Co-developed-by: Song Xue <quic_songxue@quicinc.com>
Signed-off-by: Song Xue <quic_songxue@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 78 ++++++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index b8388dcca94cd8f4e6f1360305d5f6c7fff4eec3..a5155e61f25dbfd819c67662ae471962d29d0b28 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -3079,6 +3079,22 @@ usb_1_hsphy: phy@88e2000 {
 			status = "disabled";
 		};
 
+		usb_hsphy_2: phy@88e3000 {
+			compatible = "qcom,qcs615-qusb2-phy";
+			reg = <0x0 0x088e3000 0x0 0x180>;
+
+			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "cfg_ahb",
+				      "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		usb_qmpphy: phy@88e6000 {
 			compatible = "qcom,qcs615-qmp-usb3-phy";
 			reg = <0x0 0x88e6000 0x0 0x1000>;
@@ -3168,6 +3184,68 @@ usb_1_dwc3: usb@a600000 {
 				snps,usb3_lpm_capable;
 			};
 		};
+
+		usb_2: usb@a8f8800 {
+			compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a8f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>,
+				 <&gcc GCC_USB20_SEC_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
+				 <&gcc GCC_USB20_SEC_SLEEP_CLK>,
+				 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB2_PRIM_CLKREF_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB20_SEC_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 10 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
+
+			power-domains = <&gcc USB20_SEC_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB20_SEC_BCR>;
+
+			qcom,select-utmi-as-pipe-clk;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_2_dwc3: usb@a800000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a800000 0x0 0xcd00>;
+
+				iommus = <&apps_smmu 0xe0 0x0>;
+				interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>;
+
+				phys = <&usb_hsphy_2>;
+				phy-names = "usb2-phy";
+
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+
+				maximum-speed = "high-speed";
+			};
+		};
 	};
 
 	arch_timer: timer {

-- 
2.25.1

[PATCH v3 2/2] arm64: dts: qcom: qcs615-ride: Enable secondary USB controller on QCS615 Ride

[Song Xue]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Enable secondary USB controller on QCS615 Ride platform. The secondary
USB controller is made "host", as it is a Type-A port.

Secondary USB controller of QCS615 Ride has Type-A port exposed for
connecting peripheral. The VBUS to the peripheral is provided by
TPS2549IRTERQ1 regulator connected to the port. The regulator has an
enable pin controlled by PM8150. Model it as fixed regulator and keep it
Always-On at boot, since the regulator is GPIO controlled regulator.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Co-developed-by: Song Xue <quic_songxue@quicinc.com>
Signed-off-by: Song Xue <quic_songxue@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 36 ++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index f41319ff47b983d771da52775fa78b4385c4e532..66f988104697367e87c1a9e688b3e1ff4c10a644 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -4,6 +4,7 @@
  */
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "qcs615.dtsi"
 #include "pm8150.dtsi"
@@ -33,6 +34,16 @@ xo_board_clk: xo-board-clk {
 			#clock-cells = <0>;
 		};
 	};
+
+	regulator-usb2-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "USB2_VBUS";
+		gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usb2_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		regulator-always-on;
+	};
 };
 
 &apps_rsc {
@@ -203,6 +214,15 @@ &gcc {
 		 <&sleep_clk>;
 };
 
+&pm8150_gpios {
+	usb2_en: usb2-en-state {
+		pins = "gpio10";
+		function = "normal";
+		output-enable;
+		power-source = <0>;
+	};
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
@@ -248,6 +268,22 @@ &usb_1_dwc3 {
 	dr_mode = "peripheral";
 };
 
+&usb_hsphy_2 {
+	vdd-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+	vdda-phy-dpdm-supply = <&vreg_l13a>;
+
+	status = "okay";
+};
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "host";
+};
+
 &watchdog {
 	clocks = <&sleep_clk>;
 };

-- 
2.25.1

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs615-ride: Enable secondary USB controller on QCS615 Ride

[Konrad Dybcio]

On 18.12.2024 1:12 PM, Song Xue wrote:
> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> 
> Enable secondary USB controller on QCS615 Ride platform. The secondary
> USB controller is made "host", as it is a Type-A port.
> 
> Secondary USB controller of QCS615 Ride has Type-A port exposed for
> connecting peripheral. The VBUS to the peripheral is provided by
> TPS2549IRTERQ1 regulator connected to the port. The regulator has an
> enable pin controlled by PM8150. Model it as fixed regulator and keep it
> Always-On at boot, since the regulator is GPIO controlled regulator.
> 
> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
> Signed-off-by: Song Xue <quic_songxue@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v3 0/2] arm64: dts: qcom: Add DT support for secondary USB on QCS615

[Bjorn Andersson]

On Wed, 18 Dec 2024 20:12:55 +0800, Song Xue wrote:
> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> 
> These series aim at enabling secondary USB on QCS615. The secondary
> controller is High Speed capable and has a QUSB2 Phy.
> 
> Base DT Support has been added and is enabled on Ride Platform. The
> secondary controller is enabled in host mode.
> 
> [...]

Applied, thanks!

[1/2] arm64: dts: qcom: qcs615: Add support for secondary USB node on QCS615
      commit: 2be96096148f1a8c51e4ac99753b41f4d532b99c
[2/2] arm64: dts: qcom: qcs615-ride: Enable secondary USB controller on QCS615 Ride
      commit: b8993bd786c1681ce0aa65b7a04159bf712c1e21

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>