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From: Konrad Dybcio <konradybcio@kernel.org>
To: Connor Abbott <cwabbott0@gmail.com>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: Antonino Maniscalco <antomani103@gmail.com>,
	Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/7] drm/msm: Fix bv_fence being used as bv_rptr
Date: Tue, 20 Aug 2024 13:25:50 +0200	[thread overview]
Message-ID: <f6258263-cea0-45ea-bee4-613b761fbff3@kernel.org> (raw)
In-Reply-To: <CACu1E7H6g=8thZfoRh8-svjqhdTOPg5diKoj+ENa4F5==d5RxA@mail.gmail.com>

On 20.08.2024 12:45 PM, Connor Abbott wrote:
> On Tue, Aug 20, 2024 at 11:15 AM Konrad Dybcio <konradybcio@kernel.org> wrote:
>>
>> On 15.08.2024 8:26 PM, Antonino Maniscalco wrote:
>>> The bv_fence field of rbmemptrs was being used incorrectly as the BV
>>> rptr shadow pointer in some places.
>>>
>>> Add a bv_rptr field and change the code to use that instead.
>>>
>>> Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
>>> ---
>>>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
>>>  drivers/gpu/drm/msm/msm_ringbuffer.h  | 1 +
>>>  2 files changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>> index bcaec86ac67a..32a4faa93d7f 100644
>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>> @@ -1132,7 +1132,7 @@ static int hw_init(struct msm_gpu *gpu)
>>>       /* ..which means "always" on A7xx, also for BV shadow */
>>>       if (adreno_is_a7xx(adreno_gpu)) {
>>>               gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR,
>>> -                         rbmemptr(gpu->rb[0], bv_fence));
>>> +                         rbmemptr(gpu->rb[0], bv_rptr));
>>>       }
>>>
>>>       /* Always come up on rb 0 */
>>> diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h
>>> index 0d6beb8cd39a..40791b2ade46 100644
>>> --- a/drivers/gpu/drm/msm/msm_ringbuffer.h
>>> +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h
>>> @@ -31,6 +31,7 @@ struct msm_rbmemptrs {
>>>       volatile uint32_t rptr;
>>>       volatile uint32_t fence;
>>>       /* Introduced on A7xx */
>>> +     volatile uint32_t bv_rptr;
>>
>> This is never initialized or assigned any value, no?
>>
>> Konrad
> 
> Neither is the original (retroactively BR) shadow RPTR, except
> apparently on suspend (no idea why). It's written by the GPU as it
> reads the ringbuffer, because CP_BV_RPTR_ADDR is set to its address.
> For the BV shadow RPTR, we aren't really using it for anything (and
> neither is kgsl) so we just need to point the register to a valid
> "dummy" address that isn't used by anything else.

Alright, thanks

Konrad

  reply	other threads:[~2024-08-20 11:25 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-15 18:26 [PATCH 0/7] Preemption support for A7XX Antonino Maniscalco
2024-08-15 18:26 ` [PATCH 1/7] drm/msm: Fix bv_fence being used as bv_rptr Antonino Maniscalco
2024-08-19 19:59   ` Akhil P Oommen
2024-08-20 10:09   ` Konrad Dybcio
2024-08-20 10:45     ` Connor Abbott
2024-08-20 11:25       ` Konrad Dybcio [this message]
2024-08-15 18:26 ` [PATCH 2/7] drm/msm: Add submitqueue setup and close Antonino Maniscalco
2024-08-19 20:00   ` Akhil P Oommen
2024-08-20 10:10   ` Konrad Dybcio
2024-08-20 13:49     ` Antonino Maniscalco
2024-08-15 18:26 ` [PATCH 3/7] drm/msm: Add a `preempt_record_size` field Antonino Maniscalco
2024-08-19 20:03   ` Akhil P Oommen
2024-08-15 18:26 ` [PATCH 4/7] drm/msm/A6xx: Implement preemption for A7XX targets Antonino Maniscalco
2024-08-16 12:23   ` kernel test robot
2024-08-18  0:34   ` kernel test robot
2024-08-19 20:08   ` Akhil P Oommen
2024-08-21 14:34     ` Antonino Maniscalco
2024-08-22 19:23       ` Akhil P Oommen
2024-08-23  0:19         ` Antonino Maniscalco
2024-08-21 16:02     ` Connor Abbott
2024-08-22 20:05       ` Akhil P Oommen
2024-08-23  9:21         ` Connor Abbott
2024-08-23  9:23           ` Connor Abbott
2024-08-27 19:48             ` Akhil P Oommen
2024-08-27 20:25               ` Antonino Maniscalco
2024-08-27 21:07                 ` Rob Clark
2024-08-27 22:56                   ` Antonino Maniscalco
2024-08-28 13:42                     ` Rob Clark
2024-08-28 13:46                       ` Rob Clark
2024-08-28 19:23                         ` Akhil P Oommen
2024-08-28 19:46                           ` Antonino Maniscalco
2024-08-15 18:26 ` [PATCH 5/7] drm/msm/A6xx: Add traces for preemption Antonino Maniscalco
2024-08-19 20:11   ` Akhil P Oommen
2024-08-15 18:26 ` [PATCH 6/7] drm/msm/A6XX: Add a flag to allow preemption to submitqueue_create Antonino Maniscalco
2024-08-19 20:31   ` Akhil P Oommen
2024-08-20 10:48     ` Connor Abbott
2024-08-22 19:21       ` Akhil P Oommen
2024-08-23  0:01         ` Antonino Maniscalco
2024-08-20 10:16   ` Konrad Dybcio
2024-08-20 10:18     ` Konrad Dybcio
2024-08-15 18:26 ` [PATCH 7/7] drm/msm/A6xx: Enable preemption for A7xx targets Antonino Maniscalco
2024-08-19 20:41   ` Akhil P Oommen
2024-08-16 17:47 ` [PATCH 0/7] Preemption support for A7XX Rob Clark
2024-08-16 23:42   ` Antonino Maniscalco
2024-08-23  8:22 ` neil.armstrong
2024-08-23  9:54   ` Connor Abbott
2024-08-23 10:44     ` neil.armstrong

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