Re: [PATCH v4 3/3] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2

Yixun Lan
2026-04-01T04:04:22Z

Hi Han,

On 00:27 Wed 01 Apr , Han Gao wrote:
> Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the
> OrangePi RV2 board.
>
> The board utilizes a Genesys Logic GL3523 USB3.0 hub.
>
> Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and
> PHY-related Device Tree nodes for the OrangePi RV2.
>
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
> .../boot/dts/spacemit/k1-orangepi-rv2.dts | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> index e5e358d49c09..e93e7f660820 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> @@ -23,6 +23,15 @@ chosen {
> stdout-path = "serial0";
> };
>
> + pcie_vcc_3v3: regulator-pcie-vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "pcie_vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +

I've noticed you dropped usb3_hub_5v which actually provide vbus supply..
so in current version, it will leave vbus as undetermined state - whether
vbus is on or not will depend on bootloader to enable it or not?

The best choice would be waiting for Marco's onboard-dev vbus patch[1],
while in K1 platform, we workaround it by force enabling vbus after power on
(set regulator as always-on)..

Link: https://lore.kernel.org/all/20260223-v6-16-topic-usb-onboard-dev-v5-0-28d3018a8026@pengutronix.de/ [1]

> reg_vcc_4v: regulator-vcc-4v {
> compatible = "regulator-fixed";
> regulator-name = "vcc4v0";
> @@ -44,6 +53,10 @@ led1 {
> };
> };
>
> +&combo_phy {
> + status = "okay";
> +};
> +
> &eth0 {
> phy-handle = <&rgmii0>;
> phy-mode = "rgmii-id";
> @@ -190,8 +203,63 @@ dldo6 {
> };
> };
>
> +&pcie1_phy {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_3_cfg>;
> + status = "okay";
> +};
> +
> +&pcie1_port {
> + phys = <&pcie1_phy>;
> + vpcie3v3-supply = <&pcie_vcc_3v3>;
> +};
> +
> +&pcie1 {
> + vpcie3v3-supply = <&pcie_vcc_3v3>;
> + status = "okay";
> +};
> +
> +&pcie2_phy {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie2_4_cfg>;
> + status = "okay";
> +};
> +
> +&pcie2_port {
> + phys = <&pcie2_phy>;
> + vpcie3v3-supply = <&pcie_vcc_3v3>;
> +};
> +
> +&pcie2 {
> + vpcie3v3-supply = <&pcie_vcc_3v3>;
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_2_cfg>;
> status = "okay";
> };
> +
> +&usbphy2 {
> + status = "okay";
> +};
> +
> +&usb_dwc3 {
> + dr_mode = "host";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + hub_2_0: hub@1 {
> + compatible = "usb5e3,610";
> + reg = <0x1>;
> + peer-hub = <&hub_3_0>;
> + };
> +
> + hub_3_0: hub@2 {
> + compatible = "usb5e3,620";
> + reg = <0x2>;
> + peer-hub = <&hub_2_0>;
Can you confirm all usb ports work fine with this?

> + };
> +};
> --
> 2.47.3
>

--
Yixun Lan (dlan)