From: Paolo Bonzini <pbonzini@redhat.com>
To: Liang Li <liang.z.li@intel.com>, kvm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, tglx@linutronix.de,
mingo@redhat.com, kirill.shutemov@linux.intel.com,
dave.hansen@linux.intel.com, guangrong.xiao@linux.intel.com,
rkrcmar@redhat.com
Subject: Re: [PATCH RFC 4/4] VMX: Expose the LA57 feature to VM
Date: Thu, 9 Mar 2017 16:16:37 +0100 [thread overview]
Message-ID: <f76f9689-4712-94a0-e620-d16c5c1b6b75@redhat.com> (raw)
In-Reply-To: <1483003563-25847-5-git-send-email-liang.z.li@intel.com>
On 29/12/2016 10:26, Liang Li wrote:
> - if (is_noncanonical_address(la))
> + if (is_noncanonical_address(la, virt_addr_bits(ctxt)))
Using virt_addr_bits and get_virt_addr_bits is quite a mouthful. What
about using instead a pair of functions like these:
bool is_noncanonical_address(struct kvm_vcpu *vcpu, u64 addr)
{
return addr == get_canonical(addr, get_virt_addr_bits(vcpu));
}
bool emulate_is_noncanonical_address(struct x86_emulate_ctxt *ctxt,
u64 addr)
{
return addr == get_canonical(addr, virt_addr_bits(ctxt));
}
Paolo
next prev parent reply other threads:[~2017-03-09 15:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-29 9:25 [PATCH RFC 0/4] 5-level EPT Liang Li
2016-12-29 9:26 ` [PATCH RFC 1/4] x86: Add the new CPUID and CR4 bits for 5 level page table Liang Li
2016-12-29 9:26 ` [PATCH RFC 2/4] KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL Liang Li
2017-03-09 14:39 ` Paolo Bonzini
2016-12-29 9:26 ` [PATCH RFC 3/4] KVM: MMU: Add 5 level EPT & Shadow page table support Liang Li
2017-03-09 15:12 ` Paolo Bonzini
2016-12-29 9:26 ` [PATCH RFC 4/4] VMX: Expose the LA57 feature to VM Liang Li
2017-03-09 15:16 ` Paolo Bonzini [this message]
2016-12-29 20:38 ` [PATCH RFC 0/4] 5-level EPT Valdis.Kletnieks
2016-12-30 1:26 ` Li, Liang Z
2017-01-02 10:18 ` Paolo Bonzini
2017-01-17 2:18 ` Li, Liang Z
2017-03-09 14:16 ` Paolo Bonzini
2017-03-10 8:00 ` Yu Zhang
2017-01-05 13:26 ` Kirill A. Shutemov
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