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d="scan'208";a="111032907" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Jan 2021 06:25:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 14 Jan 2021 06:25:57 -0700 Received: from tyr.hegelund-hansen.dk (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 14 Jan 2021 06:25:55 -0700 Message-ID: Subject: Re: [PATCH 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings From: Steen Hegelund To: Philipp Zabel , Rob Herring CC: Microchip Linux Driver Support , "Alexandre Belloni" , Gregory Clement , , , Date: Thu, 14 Jan 2021 14:25:54 +0100 In-Reply-To: <80d4d9b16628847c59a7f94a7c002d8ce859b0ca.camel@pengutronix.de> References: <20210113201915.2734205-1-steen.hegelund@microchip.com> <20210113201915.2734205-2-steen.hegelund@microchip.com> <80d4d9b16628847c59a7f94a7c002d8ce859b0ca.camel@pengutronix.de> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.38.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Philipp, On Thu, 2021-01-14 at 10:39 +0100, Philipp Zabel wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > Hi Steen, > > On Wed, 2021-01-13 at 21:19 +0100, Steen Hegelund wrote: > > Signed-off-by: Steen Hegelund > > --- > >  .../bindings/reset/microchip,rst.yaml         | 52 > > +++++++++++++++++++ > >  1 file changed, 52 insertions(+) > >  create mode 100644 > > Documentation/devicetree/bindings/reset/microchip,rst.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/reset/microchip,rst.yaml > > b/Documentation/devicetree/bindings/reset/microchip,rst.yaml > > new file mode 100644 > > index 000000000000..b5526753e85d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml > > @@ -0,0 +1,52 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#" > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > + > > +title: Microchip Sparx5 Switch Reset Controller > > + > > +maintainers: > > +  - Steen Hegelund > > +  - Lars Povlsen > > + > > +description: | > > +  The Microchip Sparx5 Switch provides reset control and > > implements the following > > +  functions > > +    - One Time Switch Core Reset (Soft Reset) > > + > > +properties: > > +  $nodename: > > +    pattern: "^reset-controller@[0-9a-f]+$" > > + > > +  compatible: > > +    const: microchip,sparx5-switch-reset > > + > > +  reg: > > +    maxItems: 1 > > + > > +  "#reset-cells": > > +    const: 1 > > + > > +  syscons: > > +    $ref: "/schemas/types.yaml#/definitions/phandle-array" > > +    description: Array of syscons used to access reset registers > > +    minItems: 2 > > The order seems to be important in the driver, so this should specify > which is the CPU syscon and which is the GCB syscon. I'm not sure if > it > would be better to have two separately named syscon properties with a > single phandle each. Yes you got a point. I will change that. > > regards > Philipp BR Steen