From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4348C2E2663 for ; Fri, 1 May 2026 02:08:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777601309; cv=none; b=qRINfLxqPquj1SX2d38OdNK/RmTX+qUZF2+ImA7GAmeUBGNEDUCPjtQLLK6bA/M+TtmRdMdJ4HYrFjZnhjh5CY0h4QBcs1Zfp7rlVNA9wQDQswozYhgbjpuq1m2yOImD+x8KSWYfoOPxPO60OYtoFWKRzWLeW1B/UR6FZd9WWT0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777601309; c=relaxed/simple; bh=cX6ylCwLWkbT5yjublvyn2/hVA6tirJHLb3gLL4aW00=; h=Date:From:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=LkYI/Y7CeaN6ABByq8SCuFRaJdLJXGo9p0r5zcUTmqPujBHc5OBZEqBruHTLWuAJq2lxuvKsc1CZ94Q1NrGrBoFrWZhU9QQ5MZHEf2yqk6hKeI6EeoChM+9L2XR7dFBX/AUCkhON3GLrcCbpa752v27dlYlVAd9qJAW6TdeZSLQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f8C+31Cg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f8C+31Cg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 773B0C2BCB3; Fri, 1 May 2026 02:08:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777601308; bh=cX6ylCwLWkbT5yjublvyn2/hVA6tirJHLb3gLL4aW00=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=f8C+31CgfLxwz5Ohl6uqPDEukn3RM38jRHDlJZdco/d6pgE7+EAU/NmvT3khqCPT6 iHsGOAYroi5lam7UzHeyKQsHT6I2XavVP5Y6O+6wcEH94hcWEgq+3C21e1XcHOJgRO 69/ji8cJfLYE6PrK1gMheNg7ojlyy9dApSwr1wU3mLP7DlcTJ+XBdlKAkSAJaPaAUd bF41okhbFBFuW5oHTCVmcstLYPkdaBlQ88zUtU8zIAeE/EZBYY9ft9Ck86LbnKwXvV 2z2GUUus5Mh1GOquoLUnWAoWgdcCdbAhcSTksxO4rMCP1gP3VMeSI6D7oR2JJqoXmx /gfO3QtwgoS3Q== Date: Thu, 30 Apr 2026 20:08:26 -0600 (MDT) From: Paul Walmsley To: Michael Neuling cc: =?ISO-8859-15?Q?Bj=F6rn_T=F6pel?= , "Mike Rapoport (Microsoft)" , "Vishal Moola (Oracle)" , Albert Ou , Aleksa Paunovic , Aleksandar Rikalo , Alexandre Ghiti , Andrew Jones , Andrew Morton , Arnd Bergmann , David Hildenbrand , Djordje Todorovic , Guo Ren , Junhui Liu , Kevin Brodsky , Lorenzo Stoakes , Nam Cao , Oleg Nesterov , Oscar Salvador , Palmer Dabbelt , Paul Walmsley , Qinglin Pan , Raj Vishwanathan4 , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH 1/5] riscv: errata: Fix bitwise vs logical AND in MIPS errata patching In-Reply-To: <20260409091143.1348853-2-mikey@neuling.org> Message-ID: References: <20260409091143.1348853-1-mikey@neuling.org> <20260409091143.1348853-2-mikey@neuling.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Thu, 9 Apr 2026, Michael Neuling wrote: > The condition checking whether a specific errata needs patching uses > logical AND (&&) instead of bitwise AND (&). Since logical AND only > checks that both operands are non-zero, this causes all errata patches > to be applied whenever any single errata is detected, rather than only > applying the matching one. > > The SiFive errata implementation correctly uses bitwise AND for the same > check. > > Fixes: 0b0ca959d2 ("riscv: errata: Fix the PAUSE Opcode for MIPS P8700") > Signed-off-by: Michael Neuling > Assisted-by: Cursor:claude-4.6-opus-high-thinking Thanks, after fixing the checkpatch warning regarding the Fixes: line in the patch description, queued for v7.1-rc. - Paul