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* [PATCH v2 1/6] MIPS: Sync after cacheflush on BMIPS processors
@ 2011-01-14  1:52 Kevin Cernekee
  2011-01-14  1:52 ` [PATCH v2 2/6] MIPS: pfn_valid() is broken on low memory HIGHMEM systems Kevin Cernekee
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Kevin Cernekee @ 2011-01-14  1:52 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: macro, skuribay, raiko, linux-mips, linux-kernel

On BMIPS processors, cache writeback operations may complete before the
data has actually been written out to memory.  Subsequent uncached reads
(or I/O operations) may see stale data unless a sync instruction is
executed after the writeback loop.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/include/asm/hazards.h |   21 +++++++++++++++++++++
 arch/mips/mm/c-r4k.c            |    5 +++++
 2 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 4e33216..655da05 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -270,4 +270,25 @@ ASMMACRO(disable_fpu_hazard,
 )
 #endif
 
+/*
+ * Some processors will "pipeline" cache writeback operations, and need an
+ * extra sync instruction to ensure that they are actually flushed out to
+ * memory.  Performing an uncached read (or an I/O operation) without the
+ * flush may cause stale data to be fetched.
+ */
+
+#if defined(CONFIG_CPU_BMIPS3300) || defined(CONFIG_CPU_BMIPS4350) || \
+    defined(CONFIG_CPU_BMIPS4380) || defined(CONFIG_CPU_BMIPS5000)
+
+#define cacheflush_hazard()						\
+do {									\
+	__sync();							\
+} while (0)
+
+#else
+
+#define cacheflush_hazard() do { } while (0)
+
+#endif
+
 #endif /* _ASM_HAZARDS_H */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index b4923a7..6c113cd 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -33,6 +33,7 @@
 #include <asm/mmu_context.h>
 #include <asm/war.h>
 #include <asm/cacheflush.h> /* for run_uncached() */
+#include <asm/hazards.h>
 
 
 /*
@@ -604,6 +605,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 			r4k_blast_scache();
 		else
 			blast_scache_range(addr, addr + size);
+		cacheflush_hazard();
 		return;
 	}
 
@@ -620,6 +622,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 	}
 
 	bc_wback_inv(addr, size);
+	cacheflush_hazard();
 }
 
 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
@@ -647,6 +650,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 				 (addr + size - 1) & almask);
 			blast_inv_scache_range(addr, addr + size);
 		}
+		cacheflush_hazard();
 		return;
 	}
 
@@ -663,6 +667,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 	}
 
 	bc_inv(addr, size);
+	cacheflush_hazard();
 }
 #endif /* CONFIG_DMA_NONCOHERENT */
 
-- 
1.7.0.4


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH RESEND 1/6] MIPS: sync after cacheflush
@ 2011-01-06  7:31 Kevin Cernekee
  2011-01-06  7:31 ` [PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs Kevin Cernekee
  0 siblings, 1 reply; 7+ messages in thread
From: Kevin Cernekee @ 2011-01-06  7:31 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: macro, skuribay, raiko, linux-mips, linux-kernel

On processors with deep write buffers, it is likely that many cycles
will pass between a CACHE instruction and the time the data actually
gets written out to DRAM.  Add a SYNC instruction to ensure that the
buffers get emptied before the flush functions return.

Actual problem seen in the wild:

1) dma_alloc_coherent() allocates cached memory

2) memset() is called to clear the new pages

3) dma_cache_wback_inv() is called to flush the zero data out to memory

4) dma_alloc_coherent() returns an uncached (kseg1) pointer to the
freshly allocated pages

5) Caller writes data through the kseg1 pointer

6) Buffered writeback data finally gets flushed out to DRAM

7) Part of caller's data is inexplicably zeroed out

This patch adds SYNC between steps 3 and 4, which fixed the problem.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/mm/c-r4k.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index b4923a7..dc5d9c4 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -604,6 +604,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 			r4k_blast_scache();
 		else
 			blast_scache_range(addr, addr + size);
+		__sync();
 		return;
 	}
 
@@ -620,6 +621,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 	}
 
 	bc_wback_inv(addr, size);
+	__sync();
 }
 
 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
@@ -647,6 +649,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 				 (addr + size - 1) & almask);
 			blast_inv_scache_range(addr, addr + size);
 		}
+		__sync();
 		return;
 	}
 
@@ -663,6 +666,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 	}
 
 	bc_inv(addr, size);
+	__sync();
 }
 #endif /* CONFIG_DMA_NONCOHERENT */
 
-- 
1.7.0.4


^ permalink raw reply related	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2011-01-14  1:57 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-01-14  1:52 [PATCH v2 1/6] MIPS: Sync after cacheflush on BMIPS processors Kevin Cernekee
2011-01-14  1:52 ` [PATCH v2 2/6] MIPS: pfn_valid() is broken on low memory HIGHMEM systems Kevin Cernekee
2011-01-14  1:52 ` [PATCH v2 RESEND 3/6] MIPS: Move FIXADDR_TOP into spaces.h Kevin Cernekee
2011-01-14  1:52 ` [PATCH v4 RESEND 4/6] MIPS: HIGHMEM DMA on noncoherent MIPS32 processors Kevin Cernekee
2011-01-14  1:52 ` [PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs Kevin Cernekee
2011-01-14  1:52 ` [PATCH RESEND 6/6] MIPS: Limit fixrange_init() to the FIXMAP region Kevin Cernekee
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2011-01-06  7:31 [PATCH RESEND 1/6] MIPS: sync after cacheflush Kevin Cernekee
2011-01-06  7:31 ` [PATCH RESEND 5/6] MIPS: Install handlers for BMIPS software IRQs Kevin Cernekee

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