From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29B4648986B for ; Tue, 25 Aug 2026 17:20:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787678429; cv=none; b=frDy394zMJGKUrBV6ayjkzPxVaafCoVwLRZBDv/X1sRan8sFdBWdTfThYdS0vxHC2acPOCOLYtF8cxTh1ZwhaQemuOKG+HBkuLVD21q+4kiZfeWQSOPmeBfLj17qT2R8jMP+3vn9FbBhoZErrBC2o7DbhkUsPrtko9cr7e2WAkA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787678429; c=relaxed/simple; bh=76Qfs4fzFRJFWgUkz2WuCwo5cMQXqNI3Rd1HhYdAMn0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=iaCosx47Oju1t8nixi88jk4BVcQN5pjtENUgcdNcoBd7l1uS4z3jWekzVacuf5W+TDv9yk7WJ2vsJzJwsuqpL9/hzY24o1e+ntC6ofgCGM21rdpggRkj26YZdaQIaT44pnp+Ef8D11RHvxGlB+Zn6MDG2ItWY5b3HFrJALLGPFQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IVLueRP7; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=NSoihNFr; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IVLueRP7"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="NSoihNFr" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 67PHG2lO1418178 for ; Tue, 25 Aug 2026 17:20:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= CV9FIhO/83ahE0BC2NxprFmP61XTEJfAfGCrazEmKfk=; b=IVLueRP752bURIc4 U6EYF4Z5BXBYMRTjy7ZlEufrvEvcYjD9Wou3TTZUioa0Sfpz1sVWOeb6ZH5ksOFQ Y0p8+rnG7Q2zpp0es4JAZsRjOW6GLYJYEatFEfsPlp9ZCrVQiVGYBHwF9XqaGyEA OYOP2GZV9iE1MMeCA2JLMkjwSH165VUuQAjaQpD+NUN9/1IiHK1j2vCaZ4LQY1mR e2nF54zHTUYVYnuftIQqTwdiZV/3sHgAOnCpVxk6EsEKCKiNgNlNiqtfKD1ibuun tB7jP76mZr95pAXB71s3NMNqkAEUM/+0C7K8cQk8qsiI0EDKTtxqnUjuvbJQxTPJ cyaA2A== Received: from mail-pg1-f200.google.com (mail-pg1-f200.google.com [209.85.215.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4g9f9ur0wj-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 25 Aug 2026 17:20:26 +0000 (GMT) Received: by mail-pg1-f200.google.com with SMTP id 41be03b00d2f7-cc1a439db36so2625910a12.2 for ; Tue, 25 Aug 2026 10:20:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1787678426; x=1788283226; darn=vger.kernel.org; h=content-transfer-encoding:content-type:in-reply-to:from :content-language:references:cc:to:subject:user-agent:mime-version :date:message-id:from:to:cc:subject:date:message-id:reply-to :content-type; bh=CV9FIhO/83ahE0BC2NxprFmP61XTEJfAfGCrazEmKfk=; b=NSoihNFrtxi6btSS2fAMc1WHWuxl/ceOpPMNe52paJA+9Atgi3hyjyLxrGjSPCAcX6 LBSuIom8kcvFrD6KfBDwQ1ALoGSpUwf4oYTivfV1Bw2Jdy3SnmTyrBHbMiFhDsekrI/c 5Xr+tEVtmE7RKCfkL57hN1rtBgLnjPxocC0G5i2JO/xT2Vsstl5LzfEs/vI0jmgZ2f7S I+imTrKMT/S/w0WykP0zcSGHda4mHJPLH1Z6KGZI8iM+7jJOhxDNNifkkPaP4eLdlsyQ AAoBlaRE41wvcDSTY0WPy88k7bB6cifWxYIx2JvR+QOXGOPtcTUb9ml4D92YLyjeUA6l P8UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787678426; x=1788283226; h=content-transfer-encoding:content-type:in-reply-to:from :content-language:references:cc:to:subject:user-agent:mime-version :date:message-id:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=CV9FIhO/83ahE0BC2NxprFmP61XTEJfAfGCrazEmKfk=; b=b8T9qybkjI8X8qH8L/vhCKE58SUaG4G9UN6S/655ZUb6oQ9rxE7w4+FLvr/FeolIVr XP7AOjxIO3VT8UtzLaIMsCYQ5Rq5tzdCFXVRwfTDe3I8IR75UbFcclma3eulPebubdZr HI7yNJgEP2UYccoH4iGYXuVV6hx4lWffTMRbVdSw74CnCHw0E+H+Qr5V7roxtPsQQ/T7 tYiYqivoOeid1HNvRc8+dtHiH4+OLSxuucSx/GKyZyznp5VvUYPKVadTrBBwv30AXWpD tDWIya/AMN9OQikCW/PL5l+Z7+LLUY3RRfkMd6SksppPWows70akPbN/qq6eEJM/wkEQ boJA== X-Forwarded-Encrypted: i=1; AHgh+RoYRYwxUocsJlnPQrYUL/1oOmaCO0pLDUYDmm5Lvfv3rkuYMtIOrXAVnd9wlZxVyGb66MG/9pq4wB0EYcM=@vger.kernel.org X-Gm-Message-State: AFuF++lNSKz6VBVBzEjKiDPETxTUbqlLi0OjN0kT5vEIzh8K2v2zmjXp t14E3uEM1gM/2UVuOq+HzP02IuEAtgIIe2SZvszZbBAtPLU89Mzwx8QlRi33x2TcYzFQJYygfEZ 213DlZS+YeSfnsZlG/e+TSmm7OdPUzZvazQU/jCDsLtBKnynxdLGvgdXhQsJFe7jcIx0= X-Gm-Gg: AR+sD10q33lRjE1mt64xQYJrgNU7P40etA9HKVXuQG4qoIKeDt+82a51l/stce7M+da gRHbRTzOdJsN/YfwxMyE3k58d8afcOSOKbmq2i7jaQ3y8g7M19K4pwMfv2OeH0klWVACTU/I2E6 b80bzrC7OoWOJnNqZOS0UZZREy/bpWGYpv96aLFocGRN8AgYAb9ejz3yd1xjBghWYLz5cOeYAeF MhwBnYSt3nr3vfayB7hyhQk/ovugpDo6mgS40DuhQ8CpNGcYUxfGXqG2qeGVtR/1pLFjMeHWagr YoHLrMvxKGEeR6jvnCkSaUN6JC3fWueHbOZhHmOsYrLAsN4Qiieb81Wp/zT8Ep/Zj/fEjJ6Ywu5 HaDPq4TuCrJxyghmj8RyHuMABAU/gVLPL X-Received: by 2002:a05:6a21:3398:b0:3bf:9b61:f7ae with SMTP id adf61e73a8af0-3cd9122fcd0mr14279012637.14.1787678425816; Tue, 25 Aug 2026 10:20:25 -0700 (PDT) X-Received: by 2002:a05:6a21:3398:b0:3bf:9b61:f7ae with SMTP id adf61e73a8af0-3cd9122fcd0mr14278929637.14.1787678425187; Tue, 25 Aug 2026 10:20:25 -0700 (PDT) Received: from [192.168.0.7] ([49.204.110.145]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3283d769d81sm428872eec.13.2026.08.25.10.20.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Aug 2026 10:20:24 -0700 (PDT) Message-ID: Date: Tue, 25 Aug 2026 22:50:19 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] i2c: qcom-geni: add I2C frequency table for 32 MHz firmware-based SEs To: Kathiravan Thirumoorthy , Mukesh Kumar Savaliya , Viken Dadhaniya , Andi Shyti , Manikanta Mylavarapu , Bjorn Andersson , Konrad Dybcio Cc: Mukesh Kumar Savaliya , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260812-ipq5424_i2c_scl_updates-v2-0-e09cd39d01d7@oss.qualcomm.com> <20260812-ipq5424_i2c_scl_updates-v2-2-e09cd39d01d7@oss.qualcomm.com> Content-Language: en-US From: Praveen Talari In-Reply-To: <20260812-ipq5424_i2c_scl_updates-v2-2-e09cd39d01d7@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: OMzFeLpniq-6lj72UzKHRI6jIv8m7Gia X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI1MDE0NiBTYWx0ZWRfX3qQ/cgYBTpGl Ey1rZJjqnF7nN5uohu/uKXDA22no/WlSQUIdoRYAbNbY5ddl2x/YO8g3VeTir/Vfuqq+1Oxyl/1 Ix4bNL81fj8PB0Pj+JoziC/FaQ129aayTkbcf6znaRzfPoAg3xQyu+Qsr4btrmhJ7Gigl2g/Pst N8yjTUzMwFXHUzW4s11BrnipPGKAxbFZM6HD0/DoQQR2qILliVerkZG0p+szcztfRu+NU5eb+0H pM1a3HJrBIDwJ5K6pOJfUgiC202h06QAN2ximIQ128cr1TgbYw2jbDNZPw4WFHnEKCGdxT/Pzzp 0Ia7NtQ9X+sSKiY651coHr2Nhlh5FkMcJiX43ZEoLuAkAD2kJ4jOeKOff+SKQqxxr3MZHbW3TDF gUG43IITfnSJ6x+QLGqY1rpWSvfLhhGBZKB9vhriYhGTVIgLDzErnH8UprMp/uzt6btyxD4BipI ECIlKSEgFiLXYhrSJbw== X-Authority-Analysis: v=2.4 cv=acNRWxot c=1 sm=1 tr=0 ts=6a8dceda cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=T2iwtsF3Qoe1cvxaLfjbZQ==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Z82qHJ9NIKfZ-gyr7UoA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI1MDE0NiBTYWx0ZWRfXx2gvqSPENHhj rAEOtGf2idOpJP6Ew8qIBOUxiHLy612ELCsTMPWCWt7ft8eTvtxgAZ39xhatBQ9xnr8+EBZ3Q9o tbBKBdpkWNrpY3Nj+Wlqt1FioPb7VFA= X-Proofpoint-ORIG-GUID: OMzFeLpniq-6lj72UzKHRI6jIv8m7Gia X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-25_04,2026-08-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 phishscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 spamscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608250146 Hi Kathiravan, On 12-08-2026 14:00, Kathiravan Thirumoorthy wrote: > On IPQ5424, the I2C controller can operate on both RTL-hardened SEs > and firmware-based SEs. As documented in commit 506bb2ab0075 > ("i2c: qcom-geni: Support systems with 32MHz serial engine clock"), > in IPQ5424 SEs use a 32 MHz source clock. > > The existing frequency table does not provide the required SCL timing > parameters for firmware-based SEs. Add a dedicated frequency table > using the SCL counter values recommended by the hardware design team > and select it for firmware-based SEs to achieve the target bus > frequencies. > > Move geni_i2c_clk_map_idx() from geni_i2c_resources_init() to > geni_i2c_init() to ensure SE_HW_PARAM_2 is accessed only after the > required clocks have been enabled. > > Signed-off-by: Kathiravan Thirumoorthy > --- > drivers/i2c/busses/i2c-qcom-geni.c | 25 ++++++++++++++++++------- > include/linux/soc/qcom/geni-se.h | 1 + > 2 files changed, 19 insertions(+), 7 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c > index 00013b41a6f5..15835f10b062 100644 > --- a/drivers/i2c/busses/i2c-qcom-geni.c > +++ b/drivers/i2c/busses/i2c-qcom-geni.c > @@ -187,19 +187,28 @@ static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { > }; > > /* source_clock = 32 MHz */ > -static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { > +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_minicore[] = { > { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 }, > { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, > { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, > {} > }; > > +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_fwcore[] = { > + { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 25 }, > + { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 18 }, > + { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 6, 15, 29 }, > + {} > +}; > + > static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) > { > const struct geni_i2c_clk_fld *itr; > + bool is_minicore = FIELD_GET(GEN_USE_MINICORES, > + readl_relaxed(gi2c->se.base + SE_HW_PARAM_2)); > > if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) > - itr = geni_i2c_clk_map_32mhz; > + itr = is_minicore ? geni_i2c_clk_map_32mhz_minicore : geni_i2c_clk_map_32mhz_fwcore; The source selection remains unchanged when using 32 MHz: writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); However, what about the voltage requirements associated with the higher frequency? Are they automatically managed by the underlying provider, or is additional handling needed in the driver? Reference of konrad change for CCI I2C driver for 37.5MHz with voltage requirement. https://lore.kernel.org/linux-arm-msm/20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com/ Thanks, Praveen Talari > else > itr = geni_i2c_clk_map_19p2mhz; > > @@ -1046,6 +1055,13 @@ static int geni_i2c_init(struct geni_i2c_dev *gi2c) > return ret; > } > > + ret = geni_i2c_clk_map_idx(gi2c); > + if (ret) { > + return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n", > + gi2c->clk_freq_out); > + goto err; > + } > + > proto = geni_se_read_proto(&gi2c->se); > if (proto == GENI_SE_INVALID_PROTO) { > ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); > @@ -1109,11 +1125,6 @@ static int geni_i2c_resources_init(struct geni_se *se) > if (ret) > return ret; > > - ret = geni_i2c_clk_map_idx(gi2c); > - if (ret) > - return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n", > - gi2c->clk_freq_out); > - > return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, > Bps_to_icc(gi2c->clk_freq_out)); > } > diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h > index 29a53bbc0dd4..7e8c0bb6d674 100644 > --- a/include/linux/soc/qcom/geni-se.h > +++ b/include/linux/soc/qcom/geni-se.h > @@ -331,6 +331,7 @@ struct geni_se { > #define RX_FIFO_DEPTH_SHFT 16 > > /* SE_HW_PARAM_2 fields */ > +#define GEN_USE_MINICORES BIT(12) > #define PROG_RAM_DEPTH_MSK GENMASK(10, 0) > > #define HW_VER_MAJOR_MASK GENMASK(31, 28) >