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Wed, 03 Dec 2025 03:05:10 -0800 (PST) Message-ID: Subject: Re: [PATCH v3 2/2] iio: adc: ad9467: support write/read offset From: Nuno =?ISO-8859-1?Q?S=E1?= To: Tomas Melin , Lars-Peter Clausen , Michael Hennerich , Nuno Sa , Jonathan Cameron , David Lechner , Andy Shevchenko , Alexandru Ardelean Cc: Jonathan Cameron , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Date: Wed, 03 Dec 2025 11:05:50 +0000 In-Reply-To: <20251203-ad9434-fixes-v3-2-38d14f28456f@vaisala.com> References: <20251203-ad9434-fixes-v3-0-38d14f28456f@vaisala.com> <20251203-ad9434-fixes-v3-2-38d14f28456f@vaisala.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2025-12-03 at 09:28 +0000, Tomas Melin wrote: > Support configuring output calibration value. Among the devices > currently supported by this driver, this setting is specific to > ad9434. The offset can be used to calibrate the output against > a known input. The register is called offset, but the procedure > is best mapped internally with calibbias operation. >=20 > Reviewed-by: David Lechner > Signed-off-by: Tomas Melin > --- Still don't really like the style in .info_mask_shared_by_type and=20 .info_mask_shared_by_type_available. But ok, it seems I'm the only one. So: Reviewed-by: Nuno S=C3=A1 > =C2=A0drivers/iio/adc/ad9467.c | 60 +++++++++++++++++++++++++++++++++++++= ++++++++++- > =C2=A01 file changed, 59 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c > index 2d8f8da3671dac61994a1864a82cdbef7f54c1af..48c10acb1566ba471be0804e7= c39b0b553d76188 100644 > --- a/drivers/iio/adc/ad9467.c > +++ b/drivers/iio/adc/ad9467.c > @@ -145,6 +145,7 @@ struct ad9467_chip_info { > =C2=A0 unsigned int num_lanes; > =C2=A0 unsigned int dco_en; > =C2=A0 unsigned int test_points; > + const int *offset_range; > =C2=A0 /* data clock output */ > =C2=A0 bool has_dco; > =C2=A0 bool has_dco_invert; > @@ -234,6 +235,10 @@ static int ad9467_reg_access(struct iio_dev *indio_d= ev, unsigned int reg, > =C2=A0 return 0; > =C2=A0} > =C2=A0 > +static const int ad9434_offset_range[] =3D { > + -128, 1, 127, > +}; > + > =C2=A0static const unsigned int ad9265_scale_table[][2] =3D { > =C2=A0 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, > =C2=A0}; > @@ -298,7 +303,24 @@ static void __ad9467_get_scale(struct ad9467_state *= st, int index, > =C2=A0} > =C2=A0 > =C2=A0static const struct iio_chan_spec ad9434_channels[] =3D { > - AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 12, 's'), > + { > + .type =3D IIO_VOLTAGE, > + .indexed =3D 1, > + .channel =3D 0, > + .info_mask_shared_by_type =3D > + BIT(IIO_CHAN_INFO_SCALE) | > + BIT(IIO_CHAN_INFO_SAMP_FREQ) | > + BIT(IIO_CHAN_INFO_CALIBBIAS), > + .info_mask_shared_by_type_available =3D > + BIT(IIO_CHAN_INFO_SCALE) | > + BIT(IIO_CHAN_INFO_CALIBBIAS), > + .scan_index =3D 0, > + .scan_type =3D { > + .sign =3D 's', > + .realbits =3D 12, > + .storagebits =3D 16, > + }, > + }, > =C2=A0}; > =C2=A0 > =C2=A0static const struct iio_chan_spec ad9467_channels[] =3D { > @@ -367,6 +389,7 @@ static const struct ad9467_chip_info ad9434_chip_tbl = =3D { > =C2=A0 .default_output_mode =3D AD9434_DEF_OUTPUT_MODE, > =C2=A0 .vref_mask =3D AD9434_REG_VREF_MASK, > =C2=A0 .num_lanes =3D 6, > + .offset_range =3D ad9434_offset_range, > =C2=A0}; > =C2=A0 > =C2=A0static const struct ad9467_chip_info ad9265_chip_tbl =3D { > @@ -499,6 +522,33 @@ static int ad9467_set_scale(struct ad9467_state *st,= int val, int val2) > =C2=A0 return -EINVAL; > =C2=A0} > =C2=A0 > +static int ad9467_get_offset(struct ad9467_state *st, int *val) > +{ > + int ret; > + > + ret =3D ad9467_spi_read(st, AN877_ADC_REG_OFFSET); > + if (ret < 0) > + return ret; > + *val =3D ret; > + > + return IIO_VAL_INT; > +} > + > +static int ad9467_set_offset(struct ad9467_state *st, int val) > +{ > + int ret; > + > + if (val < st->info->offset_range[0] || val > st->info->offset_range[2]) > + return -EINVAL; > + > + ret =3D ad9467_spi_write(st, AN877_ADC_REG_OFFSET, val); > + if (ret < 0) > + return ret; > + > + return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, > + AN877_ADC_TRANSFER_SYNC); > +} > + > =C2=A0static int ad9467_outputmode_set(struct ad9467_state *st, unsigned = int mode) > =C2=A0{ > =C2=A0 int ret; > @@ -802,6 +852,8 @@ static int ad9467_read_raw(struct iio_dev *indio_dev, > =C2=A0 struct ad9467_state *st =3D iio_priv(indio_dev); > =C2=A0 > =C2=A0 switch (m) { > + case IIO_CHAN_INFO_CALIBBIAS: > + return ad9467_get_offset(st, val); > =C2=A0 case IIO_CHAN_INFO_SCALE: > =C2=A0 return ad9467_get_scale(st, val, val2); > =C2=A0 case IIO_CHAN_INFO_SAMP_FREQ: > @@ -836,6 +888,8 @@ static int ad9467_write_raw(struct iio_dev *indio_dev= , > =C2=A0 int ret; > =C2=A0 > =C2=A0 switch (mask) { > + case IIO_CHAN_INFO_CALIBBIAS: > + return ad9467_set_offset(st, val); > =C2=A0 case IIO_CHAN_INFO_SCALE: > =C2=A0 return ad9467_set_scale(st, val, val2); > =C2=A0 case IIO_CHAN_INFO_SAMP_FREQ: > @@ -874,6 +928,10 @@ static int ad9467_read_avail(struct iio_dev *indio_d= ev, > =C2=A0 const struct ad9467_chip_info *info =3D st->info; > =C2=A0 > =C2=A0 switch (mask) { > + case IIO_CHAN_INFO_CALIBBIAS: > + *type =3D IIO_VAL_INT; > + *vals =3D info->offset_range; > + return IIO_AVAIL_RANGE; > =C2=A0 case IIO_CHAN_INFO_SCALE: > =C2=A0 *vals =3D (const int *)st->scales; > =C2=A0 *type =3D IIO_VAL_INT_PLUS_MICRO;