Re: [PATCH resend 5/9] MIPS: sync after cacheflush

Gleb O. Raiko
2010-10-20T07:50:31Z

On 20.10.2010 0:11, Maciej W. Rozycki wrote:
> That said, R4k DECstations seem to perform aggressive write buffering in
> the chipset and to make sure a write has propagated to an MMIO register a
> SYNC and an uncached read operation are necessary.

Just uncached read may be enough. R4k shall pull data from its store
buffer on uncached read.

> I haven't investigated DMA dependencies and I think we currently only
> have one TURBOchannel device/driver only (that is the DEFTA/defxx FDDI
> thingy) making use of the generic DMA API on DECstations. It seemed to
> work correctly the last time I tried; presumably either because the API
> Does The Right Thing, or by pure luck and right timings.

dfx_writel issues sync after store. BTW, it seems no uncached read
issued here (just mb() is used, which seems to do sync only), so either
those uncached read is not needed (unlikely) or data from dfx_writel
wait somewhere in the chipset for being pulled by subsequent reads or
writes.

Gleb.