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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: IOxKlm-OdmG03PFCf4AybAwYqGGypX-P X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDA3OCBTYWx0ZWRfXxxfakUW3dDd5 KlRdWclWsQS91g/8ZJ5GfUV23PoszjWi1iQveqeUrsklZVt5yCzCrFIzgwIju7td3UzPgEcv/J1 5pcr8zL0Dtid4XlSGeoEOE8jjbXxRZq9DPcbg8kebk0/H9RQ+rNmqi2SFuNNivbyENC1KphY+tw EcJx6vYbIRZ36yKkz8hHeycvKWxFG1ZAsVOTrlQ41hOuYhwPLMrrb+FfRpI8uLgrxrtGNI5Nz8F 83O6vx9aEFyUEB56sGgKZB8ZuDVgSH5ZRoC8cVLrpEvhQenTOvrsXjo4n6N/6OJN3mf7niSLQvV tF2wmCY44yG/veD4wsixKKOBxBqdQPCzGw3M9ghVUb5PlVfa4/VExq6dtG9zgOE5EBrp4SQP2Fn xYvDGx1cfmH/X7HeqFvSvQRHuOk4abuFu5psv3ZCAVwwx8xn53IDOn4L3jRq3M0mAmOXJcsA X-Authority-Analysis: v=2.4 cv=E8/Npbdl c=1 sm=1 tr=0 ts=6880a9a8 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=P-IC7800AAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=CvYCOFMdU_owP9l6gQwA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=d3PnA9EDa4IxuAV0gXij:22 X-Proofpoint-ORIG-GUID: IOxKlm-OdmG03PFCf4AybAwYqGGypX-P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_01,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230078 On 7/21/2025 2:49 PM, Krzysztof Kozlowski wrote: > On Wed, Jul 16, 2025 at 08:50:12PM +0530, Pankaj Patil wrote: >> From: Taniya Das >> >> The Glymur TCSR block provides CLKREF clocks for EDP, PCIe, and USB. Add >> this to the TCSR clock controller binding together with identifiers for >> the clocks >> >> Signed-off-by: Taniya Das >> Signed-off-by: Pankaj Patil > > A nit, subject: drop second/last, redundant "bindings". The > "dt-bindings" prefix is already stating that these are bindings. > See also: > https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 > > And same for documentation... > Will fix this as well. >> --- >> .../bindings/clock/qcom,sm8550-tcsr.yaml | 3 +++ >> .../dt-bindings/clock/qcom,glymur-tcsrcc.h | 24 +++++++++++++++++++ >> 2 files changed, 27 insertions(+) >> create mode 100644 include/dt-bindings/clock/qcom,glymur-tcsrcc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >> index f3afbb25e868..9fbf88836782 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >> @@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550 >> >> maintainers: >> - Bjorn Andersson >> + - Taniya Das >> >> description: | >> Qualcomm TCSR clock control module provides the clocks, resets and >> power domains on SM8550 >> >> See also: >> + - include/dt-bindings/clock/qcom,glymur-tcsr.h >> - include/dt-bindings/clock/qcom,sm8550-tcsr.h >> - include/dt-bindings/clock/qcom,sm8650-tcsr.h >> - include/dt-bindings/clock/qcom,sm8750-tcsr.h >> @@ -22,6 +24,7 @@ properties: >> compatible: >> items: >> - enum: >> + - qcom,glymur-tcsr >> - qcom,sar2130p-tcsr >> - qcom,sm8550-tcsr >> - qcom,sm8650-tcsr >> diff --git a/include/dt-bindings/clock/qcom,glymur-tcsrcc.h b/include/dt-bindings/clock/qcom,glymur-tcsrcc.h >> new file mode 100644 >> index 000000000000..72614226b113 >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,glymur-tcsrcc.h > > Filename matching compatible. > > Best regards, > Krzysztof > Yes, I will take care. -- Thanks, Taniya Das