[RFC PATCH 1/9] x86/mm: Introduce MSR_IA32_CORE_CAPABILITIES

Rik van Riel
2025-05-06T00:48:11Z

From: Yu-cheng Yu <yu-cheng.yu@intel.com>

MSR_IA32_CORE_CAPABILITIES indicates the existence of other MSRs.
Bit[1] indicates Remote Action Request (RAR) TLB registers.

Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rik van Riel <riel@surriel.com>
---
arch/x86/include/asm/msr-index.h | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ac21dc19dde2..0828b891fe2e 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -212,6 +212,12 @@
* File.
*/

+#define MSR_IA32_CORE_CAPABILITIES 0x000000cf
+#define CORE_CAP_RAR BIT(1) /*
+ * Remote Action Request. Used to directly
+ * flush the TLB on remote CPUs.
+ */
+
#define MSR_IA32_FLUSH_CMD 0x0000010b
#define L1D_FLUSH BIT(0) /*
* Writeback and invalidate the
--
2.49.0