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Date: Tue, 28 May 2024 18:14:08 +0530
From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Roger Quadros <rogerq@kernel.org>
CC: Siddharth Vadapalli <s-vadapalli@ti.com>, <nm@ti.com>, <vigneshr@ti.com>,
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Subject: Re: [PATCH v3 7/7] arm64: dts: ti: k3-j722s: Add support for PCIe0
Message-ID: <ff6cb81b-7760-4c99-9c17-907b0a31396c@ti.com>
References: <20240524090514.152727-1-s-vadapalli@ti.com>
 <20240524090514.152727-8-s-vadapalli@ti.com>
 <a6fe1fbe-681d-429b-99cc-a5f07af1cd15@kernel.org>
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X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180

On Tue, May 28, 2024 at 03:26:11PM +0300, Roger Quadros wrote:

[...]

> >  
> > +#include <dt-bindings/phy/phy-cadence.h>
> >  #include <dt-bindings/phy/phy-ti.h>
> >  
> >  /*
> > @@ -96,6 +97,35 @@ serdes1: serdes@f010000 {
> >  		};
> >  	};
> >  
> > +	pcie0_rc: pcie@f102000 {
> 
> Please split PCIe node addition in  to separate patch. hopefully you can squash it with patches that
> add USB, SERDES0 and SERDES1 to k3-j722s-main.dtsi.

I will do so in the v4 series. Thank you for reviewing and sharing your
feedback on this series.

Regards,
Siddharth.