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[2001:14ba:a0c3:3a00::b8c]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53dbd4670e6sm595236e87.159.2024.11.20.03.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Nov 2024 03:19:21 -0800 (PST) Date: Wed, 20 Nov 2024 13:19:18 +0200 From: Dmitry Baryshkov To: Neil Armstrong Cc: Akhil P Oommen , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 04/11] drm/msm: adreno: add GMU_BW_VOTE feature flag Message-ID: References: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> <20241119-topic-sm8x50-gpu-bw-vote-v2-4-4deb87be2498@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241119-topic-sm8x50-gpu-bw-vote-v2-4-4deb87be2498@linaro.org> On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote: > The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth > along the Frequency and Power Domain level, but by default we leave the > OPP core vote for the interconnect ddr path. > > While scaling via the interconnect path was sufficient, newer GPUs > like the A750 requires specific vote paremeters and bandwidth to > achieve full functionality. > > While the feature will require some data in a6xx_info, it's safer > to only enable tested platforms with this flag first. > > Add a new feature enabling DDR Bandwidth vote via GMU. Squash into the implementation patch. > > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index 4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb..394b96eb6c83354ae008b15b562bedb96cd391dd 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -58,6 +58,7 @@ enum adreno_family { > #define ADRENO_FEAT_HAS_HW_APRIV BIT(0) > #define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) > #define ADRENO_FEAT_PREEMPTION BIT(2) > +#define ADRENO_FEAT_GMU_BW_VOTE BIT(3) > > /* Helper for formating the chip_id in the way that userspace tools like > * crashdec expect. > > -- > 2.34.1 > -- With best wishes Dmitry