* [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams
@ 2025-07-17 23:28 Jessica Zhang
2025-07-17 23:28 ` [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support Jessica Zhang
` (7 more replies)
0 siblings, 8 replies; 27+ messages in thread
From: Jessica Zhang @ 2025-07-17 23:28 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Jessica Zhang, Danila Tikhonov,
cros-qcom-dts-watchers, Rob Clark
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On some MSM chipsets, the display port controller is capable of supporting
up to 4 streams.
To drive these additional streams, the pixel clocks for the corresponding
stream needs to be enabled.
Fixup the documentation of some of the bindings to clarify exactly which
stream they correspond to, then add the new bindings and device tree
changes.
---
Changes in v3:
- Fixed dtschema errors (Rob Herring)
- Documented all pixel stream clocks (Dmitry)
- Ordered compatibility list alphabetically (Dmitry)
- Dropped assigned-clocks too (Dmitry)
- Link to v2: https://lore.kernel.org/r/20250530-dp_mst_bindings-v2-0-f925464d32a8@oss.qualcomm.com
Changes in v2:
- Rebased on top of next-20250523
- Dropped merged maintainer patch
- Added a patch to make the corresponding dts change to add pixel 1
stream
- Squashed pixel 0 and pixel 1 stream binding patches (Krzysztof)
- Drop assigned-clock-parents bindings for dp-controller (Krzysztof)
- Updated dp-controller.yaml to include all chipsets that support stream
1 pixel clock (Krzysztof)
- Added missing minItems and if statement (Krzysztof)
- Link to v1: https://lore.kernel.org/r/20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com
---
Abhinav Kumar (4):
dt-bindings: Fixup x1e80100 to add DP MST support
dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding
dt-bindings: display/msm: drop assigned-clock-parents for dp controller
dt-bindings: display/msm: add stream pixel clock bindings for MST
Jessica Zhang (1):
arm64: dts: qcom: Add MST pixel streams for displayport
.../bindings/display/msm/dp-controller.yaml | 53 +++++++++++-----
.../bindings/display/msm/qcom,sa8775p-mdss.yaml | 14 +++--
.../bindings/display/msm/qcom,sar2130p-mdss.yaml | 11 ++--
.../bindings/display/msm/qcom,sc7180-mdss.yaml | 3 -
.../bindings/display/msm/qcom,sc7280-mdss.yaml | 12 ++--
.../bindings/display/msm/qcom,sm7150-mdss.yaml | 5 --
.../bindings/display/msm/qcom,sm8750-mdss.yaml | 11 ++--
.../bindings/display/msm/qcom,x1e80100-mdss.yaml | 21 +++----
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 +++++++---
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 ++-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++-
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 ++++--
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++-------
arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 ++-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 ++-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++-
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 ++++++---
include/dt-bindings/clock/qcom,dispcc-sc7280.h | 2 +
21 files changed, 235 insertions(+), 133 deletions(-)
---
base-commit: 7a88d609b069b7d2f4d10113b18fea02921bedb1
change-id: 20241202-dp_mst_bindings-7536ffc9ae2f
Best regards,
--
Jessica Zhang <jessica.zhang@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support
2025-07-17 23:28 [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Jessica Zhang
@ 2025-07-17 23:28 ` Jessica Zhang
2025-07-18 6:16 ` Krzysztof Kozlowski
2025-07-18 9:13 ` Dmitry Baryshkov
2025-07-17 23:28 ` [PATCH v3 2/5] dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding Jessica Zhang
` (6 subsequent siblings)
7 siblings, 2 replies; 27+ messages in thread
From: Jessica Zhang @ 2025-07-17 23:28 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Jessica Zhang, Danila Tikhonov,
cros-qcom-dts-watchers, Rob Clark
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Add x1e80100 to the dp-controller bindings, fix the
displayport-controller reg bindings, and drop
assigned-clock-parents/assigned-clocks
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
---
.../devicetree/bindings/display/msm/dp-controller.yaml | 2 ++
.../bindings/display/msm/qcom,x1e80100-mdss.yaml | 15 +++++----------
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 9923b065323b..4676aa8db2f4 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -29,6 +29,8 @@ properties:
- qcom,sdm845-dp
- qcom,sm8350-dp
- qcom,sm8650-dp
+ - qcom,x1e80100-dp
+
- items:
- enum:
- qcom,sar2130p-dp
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
index 3b01a0e47333..0e699de684c8 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
@@ -170,11 +170,11 @@ examples:
displayport-controller@ae90000 {
compatible = "qcom,x1e80100-dp";
- reg = <0 0xae90000 0 0x200>,
- <0 0xae90200 0 0x200>,
- <0 0xae90400 0 0x600>,
- <0 0xae91000 0 0x400>,
- <0 0xae91400 0 0x400>;
+ reg = <0xae90000 0x200>,
+ <0xae90200 0x200>,
+ <0xae90400 0x600>,
+ <0xae91000 0x400>,
+ <0xae91400 0x400>;
interrupt-parent = <&mdss>;
interrupts = <12>;
@@ -189,11 +189,6 @@ examples:
"ctrl_link_iface",
"stream_pixel";
- assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
- <&dispcc_mdss_dptx0_pixel0_clk_src>;
- assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
- <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
-
operating-points-v2 = <&mdss_dp0_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
--
2.50.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 2/5] dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding
2025-07-17 23:28 [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Jessica Zhang
2025-07-17 23:28 ` [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support Jessica Zhang
@ 2025-07-17 23:28 ` Jessica Zhang
2025-07-17 23:28 ` [PATCH v3 3/5] dt-bindings: display/msm: drop assigned-clock-parents for dp controller Jessica Zhang
` (5 subsequent siblings)
7 siblings, 0 replies; 27+ messages in thread
From: Jessica Zhang @ 2025-07-17 23:28 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Jessica Zhang, Danila Tikhonov,
cros-qcom-dts-watchers, Rob Clark
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Add DISP_CC_MDSS_DP_PIXEL1_* macros for SC7280
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
---
include/dt-bindings/clock/qcom,dispcc-sc7280.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
index a4a692c20acf..25f736629593 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sc7280.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
@@ -48,6 +48,8 @@
#define DISP_CC_MDSS_VSYNC_CLK_SRC 38
#define DISP_CC_SLEEP_CLK 39
#define DISP_CC_XO_CLK 40
+#define DISP_CC_MDSS_DP_PIXEL1_CLK 41
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 42
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
--
2.50.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 3/5] dt-bindings: display/msm: drop assigned-clock-parents for dp controller
2025-07-17 23:28 [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Jessica Zhang
2025-07-17 23:28 ` [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support Jessica Zhang
2025-07-17 23:28 ` [PATCH v3 2/5] dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding Jessica Zhang
@ 2025-07-17 23:28 ` Jessica Zhang
2025-07-18 7:32 ` Krzysztof Kozlowski
2025-07-17 23:28 ` [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST Jessica Zhang
` (4 subsequent siblings)
7 siblings, 1 reply; 27+ messages in thread
From: Jessica Zhang @ 2025-07-17 23:28 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Jessica Zhang, Danila Tikhonov,
cros-qcom-dts-watchers, Rob Clark
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Current documentation of assigned-clock-parents for dp controller does not
describe its functionality correctly making it harder to extend it for
adding multiple streams.
Instead of fixing up the documentation, drop the assigned-clock-parents
and assigned-clocks along with the usages in the chipset specific MDSS
yaml files.
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
---
.../devicetree/bindings/display/msm/dp-controller.yaml | 15 ---------------
.../bindings/display/msm/qcom,sa8775p-mdss.yaml | 4 ----
.../bindings/display/msm/qcom,sar2130p-mdss.yaml | 5 -----
.../devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml | 3 ---
.../devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ------
.../devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml | 5 -----
.../devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml | 5 -----
7 files changed, 43 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 4676aa8db2f4..d8d94f62c102 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -73,16 +73,6 @@ properties:
- const: ctrl_link_iface
- const: stream_pixel
- assigned-clocks:
- items:
- - description: link clock source
- - description: pixel clock source
-
- assigned-clock-parents:
- items:
- - description: phy 0 parent
- - description: phy 1 parent
-
phys:
maxItems: 1
@@ -209,11 +199,6 @@ examples:
"ctrl_link",
"ctrl_link_iface", "stream_pixel";
- assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
-
- assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
-
phys = <&dp_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
index 1053b3bc4908..2dc76a074da1 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -391,10 +391,6 @@ examples:
"ctrl_link_iface",
"stream_pixel";
- assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
- <&dispcc_mdss_dptx0_pixel0_clk_src>;
- assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
-
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
index 870144b53cec..eef5627133db 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
@@ -214,11 +214,6 @@ examples:
"ctrl_link_iface",
"stream_pixel";
- assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>,
- <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>;
- assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>,
- <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>;
-
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml
index 7a0555b15ddf..a2b71b476357 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml
@@ -267,9 +267,6 @@ examples:
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
clock-names = "core_iface", "core_aux", "ctrl_link",
"ctrl_link_iface", "stream_pixel";
- assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
phys = <&dp_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
index 2947f27e0585..9e52ac9c0eb4 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
@@ -296,9 +296,6 @@ examples:
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
- assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
phys = <&mdss_edp_phy>;
phy-names = "dp";
@@ -387,9 +384,6 @@ examples:
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
- assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
phys = <&dp_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml
index 13c5d5ffabde..eafea2fe1c95 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml
@@ -399,11 +399,6 @@ examples:
"ctrl_link_iface",
"stream_pixel";
- assigned-clocks = <&dispcc_mdss_dp_link_clk_src>,
- <&dispcc_mdss_dp_pixel_clk_src>;
- assigned-clock-parents = <&dp_phy 0>,
- <&dp_phy 1>;
-
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd RPMHPD_CX>;
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
index 72c70edc1fb0..0858dd61fb0f 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
@@ -408,11 +408,6 @@ examples:
"ctrl_link_iface",
"stream_pixel";
- assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>,
- <&disp_cc_mdss_dptx0_pixel0_clk_src>;
- assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
- <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
-
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
--
2.50.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST
2025-07-17 23:28 [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Jessica Zhang
` (2 preceding siblings ...)
2025-07-17 23:28 ` [PATCH v3 3/5] dt-bindings: display/msm: drop assigned-clock-parents for dp controller Jessica Zhang
@ 2025-07-17 23:28 ` Jessica Zhang
2025-07-18 7:26 ` Krzysztof Kozlowski
` (3 more replies)
2025-07-17 23:28 ` [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport Jessica Zhang
` (3 subsequent siblings)
7 siblings, 4 replies; 27+ messages in thread
From: Jessica Zhang @ 2025-07-17 23:28 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Jessica Zhang, Danila Tikhonov,
cros-qcom-dts-watchers, Rob Clark
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more,
the display port controller can support more than one pixel stream
(multi-stream transport).
These chipsets can support up to 4 stream pixel clocks for display port
controller. To support MST on these platforms, add the appropriate
stream pixel clock bindings
Since this mode is not supported on all chipsets, add exception
rules and min/max items to clearly mark which chipsets support
only SST mode (single stream) and which ones support MST.
Note: On chipsets that do support MST, the number of streams supported
can vary between controllers. For example, SA8775P supports 4 MST
streams on mdss_dp0 but only 2 streams on mdss_dp1.
In addition, many chipsets depend on the "sm8350-dp" compatibility
string but not all (ex. SM6350) support MST. Because of these reasons,
the min/maxItem for MST-supported platforms is a range of 5-8.
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
---
.../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++-
.../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++--
.../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++--
.../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++--
.../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++--
.../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++--
6 files changed, 59 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index d8d94f62c102..2893f097df82 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -58,20 +58,28 @@ properties:
maxItems: 1
clocks:
+ minItems: 5
items:
- description: AHB clock to enable register access
- description: Display Port AUX clock
- description: Display Port Link clock
- description: Link interface clock between DP and PHY
- - description: Display Port Pixel clock
+ - description: Display Port stream 0 Pixel clock
+ - description: Display Port stream 1 Pixel clock
+ - description: Display Port stream 2 Pixel clock
+ - description: Display Port stream 3 Pixel clock
clock-names:
+ minItems: 5
items:
- const: core_iface
- const: core_aux
- const: ctrl_link
- const: ctrl_link_iface
- const: stream_pixel
+ - const: stream_1_pixel
+ - const: stream_2_pixel
+ - const: stream_3_pixel
phys:
maxItems: 1
@@ -173,6 +181,32 @@ allOf:
required:
- "#sound-dai-cells"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-dp
+ - qcom,sc7280-dp
+ - qcom,sc8180x-dp
+ - qcom,sc8280xp-dp
+ - qcom,sc8280xp-edp
+ - qcom,sm8150-dp
+ - qcom,sm8350-dp
+ - qcom,sm8650-dp
+ - qcom,x1e80100-dp
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 8
+
+ else:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+
additionalProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
index 2dc76a074da1..0af1e5cd1691 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -384,12 +384,18 @@ examples:
<&dispcc_dptx0_aux_clk>,
<&dispcc_dptx0_link_clk>,
<&dispcc_dptx0_link_intf_clk>,
- <&dispcc_dptx0_pixel0_clk>;
+ <&dispcc_dptx0_pixel0_clk>,
+ <&dispcc_dptx0_pixel1_clk>,
+ <&dispcc_dptx0_pixel2_clk>,
+ <&dispcc_dptx0_pixel3_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
index eef5627133db..0a8bda583469 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
@@ -207,12 +207,14 @@ examples:
<&dispcc_disp_cc_mdss_dptx0_aux_clk>,
<&dispcc_disp_cc_mdss_dptx0_link_clk>,
<&dispcc_disp_cc_mdss_dptx0_link_intf_clk>,
- <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>;
+ <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>,
+ <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
index 9e52ac9c0eb4..f8fffc168a71 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
@@ -378,12 +378,14 @@ examples:
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
phys = <&dp_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
index 0858dd61fb0f..0bc0edc41341 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
@@ -401,12 +401,14 @@ examples:
<&disp_cc_mdss_dptx0_aux_clk>,
<&disp_cc_mdss_dptx0_link_clk>,
<&disp_cc_mdss_dptx0_link_intf_clk>,
- <&disp_cc_mdss_dptx0_pixel0_clk>;
+ <&disp_cc_mdss_dptx0_pixel0_clk>,
+ <&disp_cc_mdss_dptx0_pixel1_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
operating-points-v2 = <&dp_opp_table>;
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
index 0e699de684c8..ceb3a0b70799 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
@@ -183,11 +183,13 @@ examples:
<&dispcc_dptx0_aux_clk>,
<&dispcc_dptx0_link_clk>,
<&dispcc_dptx0_link_intf_clk>,
- <&dispcc_dptx0_pixel0_clk>;
+ <&dispcc_dptx0_pixel0_clk>,
+ <&dispcc_dptx0_pixel1_clk>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
operating-points-v2 = <&mdss_dp0_opp_table>;
--
2.50.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport
2025-07-17 23:28 [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Jessica Zhang
` (3 preceding siblings ...)
2025-07-17 23:28 ` [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST Jessica Zhang
@ 2025-07-17 23:28 ` Jessica Zhang
2025-07-18 9:20 ` Dmitry Baryshkov
2025-07-18 9:23 ` Konrad Dybcio
2025-07-18 9:22 ` [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Dmitry Baryshkov
` (2 subsequent siblings)
7 siblings, 2 replies; 27+ messages in thread
From: Jessica Zhang @ 2025-07-17 23:28 UTC (permalink / raw)
To: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Jessica Zhang, Danila Tikhonov,
cros-qcom-dts-watchers, Rob Clark
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
The following chipsets support 2 total pixel streams:
- sa8775p (on mdss_dp1)
- sc8180x
- sc8280xp (mdss_dp0-2 only)
- sm8150
- sm8350
- sm8450
- sm8650
- x1e80100
The following chipset also supports 4 total pixel streams:
- sa8775p (mdss_dp0 only)
Add the appropriate amount of pixel stream clocks for their respective
displayport-controllers.
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 ++++++++++++----
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 +++++++---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++++++++++-----------
arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 +++++++++-----
12 files changed, 167 insertions(+), 69 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 45f536633f64..2c85eb2fc79a 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -4237,15 +4237,28 @@ mdss0_dp0: displayport-controller@af54000 {
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp0_phy 0>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>;
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
@@ -4316,15 +4329,20 @@ mdss0_dp1: displayport-controller@af5c000 {
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp1_phy 0>,
+ <&mdss0_dp1_phy 1>,
+ <&mdss0_dp1_phy 1>;
phys = <&mdss0_dp1_phy>;
phy-names = "dp";
diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index b0e342810ae7..96090a948ade 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -2139,16 +2139,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b1cc3bc1aec8..48b6a17dcea0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -5012,15 +5012,19 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index b84e47a461a0..ca188c7f1f26 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -3233,16 +3233,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
@@ -3311,16 +3315,20 @@ mdss_dp1: displayport-controller@ae98000 {
<&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 87555a119d94..11ea2fa0b853 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4338,15 +4338,19 @@ mdss0_dp0: displayport-controller@ae90000 {
<&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
@@ -4417,14 +4421,18 @@ mdss0_dp1: displayport-controller@ae98000 {
<&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
@@ -4494,10 +4502,12 @@ mdss0_dp2: displayport-controller@ae9a000 {
<&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
- <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss0>;
interrupts = <14>;
phys = <&mdss0_dp2_phy>;
@@ -4505,8 +4515,11 @@ mdss0_dp2: displayport-controller@ae9a000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
- <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp2_phy 0>,
+ <&mdss0_dp2_phy 1>,
+ <&mdss0_dp2_phy 1>;
operating-points-v2 = <&mdss0_dp2_opp_table>;
#sound-dai-cells = <0>;
@@ -5669,10 +5682,12 @@ mdss1_dp0: displayport-controller@22090000 {
<&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <12>;
phys = <&mdss1_dp0_phy>;
@@ -5680,8 +5695,11 @@ mdss1_dp0: displayport-controller@22090000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp0_phy 0>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>;
operating-points-v2 = <&mdss1_dp0_opp_table>;
#sound-dai-cells = <0>;
@@ -5741,10 +5759,12 @@ mdss1_dp1: displayport-controller@22098000 {
<&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <13>;
phys = <&mdss1_dp1_phy>;
@@ -5752,8 +5772,11 @@ mdss1_dp1: displayport-controller@22098000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp1_phy 0>,
+ <&mdss1_dp1_phy 1>,
+ <&mdss1_dp1_phy 1>;
operating-points-v2 = <&mdss1_dp1_opp_table>;
#sound-dai-cells = <0>;
@@ -5813,10 +5836,12 @@ mdss1_dp2: displayport-controller@2209a000 {
<&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
- <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <14>;
phys = <&mdss1_dp2_phy>;
@@ -5824,8 +5849,11 @@ mdss1_dp2: displayport-controller@2209a000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
- <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp2_phy 0>,
+ <&mdss1_dp2_phy 1>,
+ <&mdss1_dp2_phy 1>;
operating-points-v2 = <&mdss1_dp2_opp_table>;
#sound-dai-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index cdb47359c4c8..3a21a2e2c04d 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3894,16 +3894,20 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index f0d18fd37aaf..fc7c610c15d2 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4774,16 +4774,20 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 971c828a7555..6a930292edd3 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2872,16 +2872,20 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 54c6d0fdb2af..b0680ef30c1f 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3431,16 +3431,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 71a7e3b57ece..226c457338d9 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3545,16 +3545,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 495ea9bfd008..72c63afe9029 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5388,16 +5388,20 @@ mdss_dp0: displayport-controller@af54000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&dp_opp_table>;
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index a8eb4c5fe99f..e86b6cb20096 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5306,16 +5306,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp0_opp_table>;
@@ -5389,16 +5393,20 @@ mdss_dp1: displayport-controller@ae98000 {
<&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp1_opp_table>;
@@ -5472,16 +5480,20 @@ mdss_dp2: displayport-controller@ae9a000 {
<&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp2_opp_table>;
--
2.50.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support
2025-07-17 23:28 ` [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support Jessica Zhang
@ 2025-07-18 6:16 ` Krzysztof Kozlowski
2025-07-18 16:38 ` Jessica Zhang
2025-07-18 9:13 ` Dmitry Baryshkov
1 sibling, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-18 6:16 UTC (permalink / raw)
To: Jessica Zhang, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Abel Vesa,
Bjorn Andersson, Michael Turquette, Stephen Boyd, Mahadevan,
Krishna Manikandan, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Danila Tikhonov, cros-qcom-dts-watchers
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Yongxing Mou
On 18/07/2025 01:28, Jessica Zhang wrote:
> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> Add x1e80100 to the dp-controller bindings, fix the
> displayport-controller reg bindings, and drop
> assigned-clock-parents/assigned-clocks
>
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
That's not a correct tag really - drop the quotes. If this was added by
b4, I think you might be using an older version.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST
2025-07-17 23:28 ` [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST Jessica Zhang
@ 2025-07-18 7:26 ` Krzysztof Kozlowski
2025-07-18 9:14 ` Dmitry Baryshkov
` (2 subsequent siblings)
3 siblings, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-18 7:26 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Yongxing Mou
On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote:
> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more,
> the display port controller can support more than one pixel stream
> (multi-stream transport).
>
> These chipsets can support up to 4 stream pixel clocks for display port
> controller. To support MST on these platforms, add the appropriate
> stream pixel clock bindings
>
> Since this mode is not supported on all chipsets, add exception
> rules and min/max items to clearly mark which chipsets support
> only SST mode (single stream) and which ones support MST.
>
> Note: On chipsets that do support MST, the number of streams supported
> can vary between controllers. For example, SA8775P supports 4 MST
> streams on mdss_dp0 but only 2 streams on mdss_dp1.
>
> In addition, many chipsets depend on the "sm8350-dp" compatibility
> string but not all (ex. SM6350) support MST. Because of these reasons,
> the min/maxItem for MST-supported platforms is a range of 5-8.
Then you need to rework if:. Don't use contains for the sm8350-dp, but
list the front compatibles supporting.
>
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
> ---
> .../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++-
> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++--
> .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++--
> 6 files changed, 59 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> index d8d94f62c102..2893f097df82 100644
> --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> @@ -58,20 +58,28 @@ properties:
> maxItems: 1
>
> clocks:
> + minItems: 5
> items:
> - description: AHB clock to enable register access
> - description: Display Port AUX clock
> - description: Display Port Link clock
> - description: Link interface clock between DP and PHY
> - - description: Display Port Pixel clock
> + - description: Display Port stream 0 Pixel clock
> + - description: Display Port stream 1 Pixel clock
> + - description: Display Port stream 2 Pixel clock
> + - description: Display Port stream 3 Pixel clock
>
> clock-names:
> + minItems: 5
> items:
> - const: core_iface
> - const: core_aux
> - const: ctrl_link
> - const: ctrl_link_iface
> - const: stream_pixel
> + - const: stream_1_pixel
> + - const: stream_2_pixel
> + - const: stream_3_pixel
>
> phys:
> maxItems: 1
> @@ -173,6 +181,32 @@ allOf:
> required:
> - "#sound-dai-cells"
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sa8775p-dp
> + - qcom,sc7280-dp
> + - qcom,sc8180x-dp
> + - qcom,sc8280xp-dp
> + - qcom,sc8280xp-edp
> + - qcom,sm8150-dp
> + - qcom,sm8350-dp
> + - qcom,sm8650-dp
> + - qcom,x1e80100-dp
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + maxItems: 8
This if is redundant, drop.
> +
> + else:
> + properties:
> + clocks:
> + minItems: 5
> + maxItems: 5
Only this part has an actual effect.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 3/5] dt-bindings: display/msm: drop assigned-clock-parents for dp controller
2025-07-17 23:28 ` [PATCH v3 3/5] dt-bindings: display/msm: drop assigned-clock-parents for dp controller Jessica Zhang
@ 2025-07-18 7:32 ` Krzysztof Kozlowski
0 siblings, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-18 7:32 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Yongxing Mou
On Thu, Jul 17, 2025 at 04:28:45PM -0700, Jessica Zhang wrote:
> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> Current documentation of assigned-clock-parents for dp controller does not
> describe its functionality correctly making it harder to extend it for
It does...
> adding multiple streams.
Just extend the list?
>
> Instead of fixing up the documentation, drop the assigned-clock-parents
> and assigned-clocks along with the usages in the chipset specific MDSS
> yaml files.
It should not be added here at all, but since Qualcomm added it, it is
an ABI, so explain why this cannot be fixed or impact of this ABI
change. It is fine to drop it in general, but reasoning in first
paragraph feels incomplete. I don't see any problem in how it describes
the functionality (except that it should not be there...)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support
2025-07-17 23:28 ` [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support Jessica Zhang
2025-07-18 6:16 ` Krzysztof Kozlowski
@ 2025-07-18 9:13 ` Dmitry Baryshkov
2025-07-19 0:16 ` Jessica Zhang
1 sibling, 1 reply; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-07-18 9:13 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On Thu, Jul 17, 2025 at 04:28:43PM -0700, Jessica Zhang wrote:
> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Please fix the patch subject.
>
> Add x1e80100 to the dp-controller bindings, fix the
> displayport-controller reg bindings, and drop
> assigned-clock-parents/assigned-clocks
Why?
>
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
> ---
> .../devicetree/bindings/display/msm/dp-controller.yaml | 2 ++
> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 15 +++++----------
Split into two commits.
> 2 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> index 9923b065323b..4676aa8db2f4 100644
> --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> @@ -29,6 +29,8 @@ properties:
> - qcom,sdm845-dp
> - qcom,sm8350-dp
> - qcom,sm8650-dp
> + - qcom,x1e80100-dp
> +
> - items:
> - enum:
> - qcom,sar2130p-dp
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
> index 3b01a0e47333..0e699de684c8 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
> @@ -170,11 +170,11 @@ examples:
>
> displayport-controller@ae90000 {
> compatible = "qcom,x1e80100-dp";
> - reg = <0 0xae90000 0 0x200>,
> - <0 0xae90200 0 0x200>,
> - <0 0xae90400 0 0x600>,
> - <0 0xae91000 0 0x400>,
> - <0 0xae91400 0 0x400>;
> + reg = <0xae90000 0x200>,
> + <0xae90200 0x200>,
> + <0xae90400 0x600>,
> + <0xae91000 0x400>,
> + <0xae91400 0x400>;
>
> interrupt-parent = <&mdss>;
> interrupts = <12>;
> @@ -189,11 +189,6 @@ examples:
> "ctrl_link_iface",
> "stream_pixel";
>
> - assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
> - <&dispcc_mdss_dptx0_pixel0_clk_src>;
> - assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> - <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> -
> operating-points-v2 = <&mdss_dp0_opp_table>;
>
> power-domains = <&rpmhpd RPMHPD_MMCX>;
>
> --
> 2.50.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST
2025-07-17 23:28 ` [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST Jessica Zhang
2025-07-18 7:26 ` Krzysztof Kozlowski
@ 2025-07-18 9:14 ` Dmitry Baryshkov
2025-07-18 9:16 ` Dmitry Baryshkov
2025-07-24 11:55 ` Dmitry Baryshkov
3 siblings, 0 replies; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-07-18 9:14 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote:
> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more,
> the display port controller can support more than one pixel stream
> (multi-stream transport).
>
> These chipsets can support up to 4 stream pixel clocks for display port
> controller. To support MST on these platforms, add the appropriate
> stream pixel clock bindings
>
> Since this mode is not supported on all chipsets, add exception
> rules and min/max items to clearly mark which chipsets support
> only SST mode (single stream) and which ones support MST.
>
> Note: On chipsets that do support MST, the number of streams supported
> can vary between controllers. For example, SA8775P supports 4 MST
> streams on mdss_dp0 but only 2 streams on mdss_dp1.
>
> In addition, many chipsets depend on the "sm8350-dp" compatibility
> string but not all (ex. SM6350) support MST. Because of these reasons,
> the min/maxItem for MST-supported platforms is a range of 5-8.
>
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
> ---
> .../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++-
> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++--
> .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++--
> 6 files changed, 59 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> index d8d94f62c102..2893f097df82 100644
> --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> @@ -58,20 +58,28 @@ properties:
> maxItems: 1
>
> clocks:
> + minItems: 5
> items:
> - description: AHB clock to enable register access
> - description: Display Port AUX clock
> - description: Display Port Link clock
> - description: Link interface clock between DP and PHY
> - - description: Display Port Pixel clock
> + - description: Display Port stream 0 Pixel clock
> + - description: Display Port stream 1 Pixel clock
> + - description: Display Port stream 2 Pixel clock
> + - description: Display Port stream 3 Pixel clock
>
> clock-names:
> + minItems: 5
> items:
> - const: core_iface
> - const: core_aux
> - const: ctrl_link
> - const: ctrl_link_iface
> - const: stream_pixel
> + - const: stream_1_pixel
> + - const: stream_2_pixel
> + - const: stream_3_pixel
>
> phys:
> maxItems: 1
> @@ -173,6 +181,32 @@ allOf:
> required:
> - "#sound-dai-cells"
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sa8775p-dp
> + - qcom,sc7280-dp
> + - qcom,sc8180x-dp
> + - qcom,sc8280xp-dp
> + - qcom,sc8280xp-edp
> + - qcom,sm8150-dp
> + - qcom,sm8350-dp
> + - qcom,sm8650-dp
> + - qcom,x1e80100-dp
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + maxItems: 8
The hardware can't have variable list of clocks. Please describe the
hardware here, specifying exact number of clocks to be used.
> +
> + else:
> + properties:
> + clocks:
> + minItems: 5
> + maxItems: 5
> +
> additionalProperties: false
>
> examples:
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST
2025-07-17 23:28 ` [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST Jessica Zhang
2025-07-18 7:26 ` Krzysztof Kozlowski
2025-07-18 9:14 ` Dmitry Baryshkov
@ 2025-07-18 9:16 ` Dmitry Baryshkov
2025-07-24 11:55 ` Dmitry Baryshkov
3 siblings, 0 replies; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-07-18 9:16 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote:
> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more,
> the display port controller can support more than one pixel stream
> (multi-stream transport).
>
> These chipsets can support up to 4 stream pixel clocks for display port
> controller. To support MST on these platforms, add the appropriate
> stream pixel clock bindings
>
> Since this mode is not supported on all chipsets, add exception
> rules and min/max items to clearly mark which chipsets support
> only SST mode (single stream) and which ones support MST.
>
> Note: On chipsets that do support MST, the number of streams supported
> can vary between controllers. For example, SA8775P supports 4 MST
> streams on mdss_dp0 but only 2 streams on mdss_dp1.
Then for this platform it should be oneOf: minItems: 6 / minItems: 8
>
> In addition, many chipsets depend on the "sm8350-dp" compatibility
> string but not all (ex. SM6350) support MST. Because of these reasons,
> the min/maxItem for MST-supported platforms is a range of 5-8.
Do we still consider them to be compatible?
>
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
> ---
> .../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++-
> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++--
> .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++--
> 6 files changed, 59 insertions(+), 11 deletions(-)
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport
2025-07-17 23:28 ` [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport Jessica Zhang
@ 2025-07-18 9:20 ` Dmitry Baryshkov
2025-07-18 16:35 ` Jessica Zhang
2025-07-18 9:23 ` Konrad Dybcio
1 sibling, 1 reply; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-07-18 9:20 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On Thu, Jul 17, 2025 at 04:28:47PM -0700, Jessica Zhang wrote:
> The following chipsets support 2 total pixel streams:
> - sa8775p (on mdss_dp1)
Uppercase chipset names.
> - sc8180x
> - sc8280xp (mdss_dp0-2 only)
> - sm8150
> - sm8350
It's very strange that SM8150 and SM8350 support MST, but SM8250
doesn't. Are you sure? Your patch contradicts this.
> - sm8450
> - sm8650
> - x1e80100
>
> The following chipset also supports 4 total pixel streams:
> - sa8775p (mdss_dp0 only)
>
> Add the appropriate amount of pixel stream clocks for their respective
s/amount/number/, it's countable.
> displayport-controllers.
>
> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 ++++++++++++----
> arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 +++--
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 +++--
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 +++++++---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++++++++++-----------
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +++--
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +++--
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 +++--
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 +++--
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +++--
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +++--
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 +++++++++-----
> 12 files changed, 167 insertions(+), 69 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 45f536633f64..2c85eb2fc79a 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -4237,15 +4237,28 @@ mdss0_dp0: displayport-controller@af54000 {
> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel",
> + "stream_2_pixel",
> + "stream_3_pixel";
> assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp0_phy 0>,
> + <&mdss0_dp0_phy 1>,
> + <&mdss0_dp0_phy 1>,
> + <&mdss0_dp0_phy 1>,
> + <&mdss0_dp0_phy 1>;
> phys = <&mdss0_dp0_phy>;
> phy-names = "dp";
>
> @@ -4316,15 +4329,20 @@ mdss0_dp1: displayport-controller@af5c000 {
> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
> assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
> - assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp1_phy 0>,
> + <&mdss0_dp1_phy 1>,
> + <&mdss0_dp1_phy 1>;
> phys = <&mdss0_dp1_phy>;
> phy-names = "dp";
>
> diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
> index b0e342810ae7..96090a948ade 100644
> --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
> @@ -2139,16 +2139,20 @@ mdss_dp0: displayport-controller@ae90000 {
> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index b1cc3bc1aec8..48b6a17dcea0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -5012,15 +5012,19 @@ mdss_dp: displayport-controller@ae90000 {
> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> phy-names = "dp";
> diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> index b84e47a461a0..ca188c7f1f26 100644
> --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> @@ -3233,16 +3233,20 @@ mdss_dp0: displayport-controller@ae90000 {
> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
> @@ -3311,16 +3315,20 @@ mdss_dp1: displayport-controller@ae98000 {
> <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 87555a119d94..11ea2fa0b853 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -4338,15 +4338,19 @@ mdss0_dp0: displayport-controller@ae90000 {
> <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
> <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
> <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
> clock-names = "core_iface", "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
> @@ -4417,14 +4421,18 @@ mdss0_dp1: displayport-controller@ae98000 {
> <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
> <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
> <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
> clock-names = "core_iface", "core_aux",
> "ctrl_link",
> - "ctrl_link_iface", "stream_pixel";
> + "ctrl_link_iface", "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> @@ -4494,10 +4502,12 @@ mdss0_dp2: displayport-controller@ae9a000 {
> <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
> <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
> <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
> - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
> clock-names = "core_iface", "core_aux",
> "ctrl_link",
> - "ctrl_link_iface", "stream_pixel";
> + "ctrl_link_iface", "stream_pixel",
> + "stream_1_pixel";
> interrupt-parent = <&mdss0>;
> interrupts = <14>;
> phys = <&mdss0_dp2_phy>;
> @@ -4505,8 +4515,11 @@ mdss0_dp2: displayport-controller@ae9a000 {
> power-domains = <&rpmhpd SC8280XP_MMCX>;
>
> assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
> - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
> - assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
> + assigned-clock-parents = <&mdss0_dp2_phy 0>,
> + <&mdss0_dp2_phy 1>,
> + <&mdss0_dp2_phy 1>;
> operating-points-v2 = <&mdss0_dp2_opp_table>;
>
> #sound-dai-cells = <0>;
> @@ -5669,10 +5682,12 @@ mdss1_dp0: displayport-controller@22090000 {
> <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
> <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
> <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
> clock-names = "core_iface", "core_aux",
> "ctrl_link",
> - "ctrl_link_iface", "stream_pixel";
> + "ctrl_link_iface", "stream_pixel",
> + "stream_1_pixel";
> interrupt-parent = <&mdss1>;
> interrupts = <12>;
> phys = <&mdss1_dp0_phy>;
> @@ -5680,8 +5695,11 @@ mdss1_dp0: displayport-controller@22090000 {
> power-domains = <&rpmhpd SC8280XP_MMCX>;
>
> assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> - assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
> + assigned-clock-parents = <&mdss1_dp0_phy 0>,
> + <&mdss1_dp0_phy 1>,
> + <&mdss1_dp0_phy 1>;
> operating-points-v2 = <&mdss1_dp0_opp_table>;
>
> #sound-dai-cells = <0>;
> @@ -5741,10 +5759,12 @@ mdss1_dp1: displayport-controller@22098000 {
> <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
> <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
> <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
> clock-names = "core_iface", "core_aux",
> "ctrl_link",
> - "ctrl_link_iface", "stream_pixel";
> + "ctrl_link_iface", "stream_pixel",
> + "stream_1_pixel";
> interrupt-parent = <&mdss1>;
> interrupts = <13>;
> phys = <&mdss1_dp1_phy>;
> @@ -5752,8 +5772,11 @@ mdss1_dp1: displayport-controller@22098000 {
> power-domains = <&rpmhpd SC8280XP_MMCX>;
>
> assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
> - assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
> + assigned-clock-parents = <&mdss1_dp1_phy 0>,
> + <&mdss1_dp1_phy 1>,
> + <&mdss1_dp1_phy 1>;
> operating-points-v2 = <&mdss1_dp1_opp_table>;
>
> #sound-dai-cells = <0>;
> @@ -5813,10 +5836,12 @@ mdss1_dp2: displayport-controller@2209a000 {
> <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
> <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
> <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
> - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
> clock-names = "core_iface", "core_aux",
> "ctrl_link",
> - "ctrl_link_iface", "stream_pixel";
> + "ctrl_link_iface", "stream_pixel",
> + "stream_1_pixel";
> interrupt-parent = <&mdss1>;
> interrupts = <14>;
> phys = <&mdss1_dp2_phy>;
> @@ -5824,8 +5849,11 @@ mdss1_dp2: displayport-controller@2209a000 {
> power-domains = <&rpmhpd SC8280XP_MMCX>;
>
> assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
> - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
> - assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
> + assigned-clock-parents = <&mdss1_dp2_phy 0>,
> + <&mdss1_dp2_phy 1>,
> + <&mdss1_dp2_phy 1>;
> operating-points-v2 = <&mdss1_dp2_opp_table>;
>
> #sound-dai-cells = <0>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index cdb47359c4c8..3a21a2e2c04d 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -3894,16 +3894,20 @@ mdss_dp: displayport-controller@ae90000 {
> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index f0d18fd37aaf..fc7c610c15d2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -4774,16 +4774,20 @@ mdss_dp: displayport-controller@ae90000 {
> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 971c828a7555..6a930292edd3 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -2872,16 +2872,20 @@ mdss_dp: displayport-controller@ae90000 {
> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 54c6d0fdb2af..b0680ef30c1f 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -3431,16 +3431,20 @@ mdss_dp0: displayport-controller@ae90000 {
> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 71a7e3b57ece..226c457338d9 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -3545,16 +3545,20 @@ mdss_dp0: displayport-controller@ae90000 {
> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 495ea9bfd008..72c63afe9029 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -5388,16 +5388,20 @@ mdss_dp0: displayport-controller@af54000 {
> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> operating-points-v2 = <&dp_opp_table>;
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index a8eb4c5fe99f..e86b6cb20096 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -5306,16 +5306,20 @@ mdss_dp0: displayport-controller@ae90000 {
> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> operating-points-v2 = <&mdss_dp0_opp_table>;
> @@ -5389,16 +5393,20 @@ mdss_dp1: displayport-controller@ae98000 {
> <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> operating-points-v2 = <&mdss_dp1_opp_table>;
> @@ -5472,16 +5480,20 @@ mdss_dp2: displayport-controller@ae9a000 {
> <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
> <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
> - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
> clock-names = "core_iface",
> "core_aux",
> "ctrl_link",
> "ctrl_link_iface",
> - "stream_pixel";
> + "stream_pixel",
> + "stream_1_pixel";
>
> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
> - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
> assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>
> operating-points-v2 = <&mdss_dp2_opp_table>;
>
> --
> 2.50.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams
2025-07-17 23:28 [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Jessica Zhang
` (4 preceding siblings ...)
2025-07-17 23:28 ` [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport Jessica Zhang
@ 2025-07-18 9:22 ` Dmitry Baryshkov
2025-07-18 16:43 ` Jessica Zhang
2025-07-19 9:14 ` [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P Dmitry Baryshkov
2025-07-20 0:06 ` [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Rob Herring (Arm)
7 siblings, 1 reply; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-07-18 9:22 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On Thu, Jul 17, 2025 at 04:28:42PM -0700, Jessica Zhang wrote:
> On some MSM chipsets, the display port controller is capable of supporting
> up to 4 streams.
>
> To drive these additional streams, the pixel clocks for the corresponding
> stream needs to be enabled.
>
> Fixup the documentation of some of the bindings to clarify exactly which
> stream they correspond to, then add the new bindings and device tree
> changes.
>
> ---
> Changes in v3:
> - Fixed dtschema errors (Rob Herring)
> - Documented all pixel stream clocks (Dmitry)
> - Ordered compatibility list alphabetically (Dmitry)
> - Dropped assigned-clocks too (Dmitry)
> - Link to v2: https://lore.kernel.org/r/20250530-dp_mst_bindings-v2-0-f925464d32a8@oss.qualcomm.com
>
> Changes in v2:
> - Rebased on top of next-20250523
> - Dropped merged maintainer patch
> - Added a patch to make the corresponding dts change to add pixel 1
> stream
> - Squashed pixel 0 and pixel 1 stream binding patches (Krzysztof)
> - Drop assigned-clock-parents bindings for dp-controller (Krzysztof)
> - Updated dp-controller.yaml to include all chipsets that support stream
> 1 pixel clock (Krzysztof)
> - Added missing minItems and if statement (Krzysztof)
> - Link to v1: https://lore.kernel.org/r/20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com
>
> ---
> Abhinav Kumar (4):
> dt-bindings: Fixup x1e80100 to add DP MST support
> dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding
> dt-bindings: display/msm: drop assigned-clock-parents for dp controller
> dt-bindings: display/msm: add stream pixel clock bindings for MST
>
> Jessica Zhang (1):
> arm64: dts: qcom: Add MST pixel streams for displayport
>
> .../bindings/display/msm/dp-controller.yaml | 53 +++++++++++-----
> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 14 +++--
> .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 11 ++--
> .../bindings/display/msm/qcom,sc7180-mdss.yaml | 3 -
> .../bindings/display/msm/qcom,sc7280-mdss.yaml | 12 ++--
> .../bindings/display/msm/qcom,sm7150-mdss.yaml | 5 --
> .../bindings/display/msm/qcom,sm8750-mdss.yaml | 11 ++--
> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 21 +++----
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 +++++++---
> arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 ++++--
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++-------
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 ++++++---
> include/dt-bindings/clock/qcom,dispcc-sc7280.h | 2 +
> 21 files changed, 235 insertions(+), 133 deletions(-)
> ---
> base-commit: 7a88d609b069b7d2f4d10113b18fea02921bedb1
Can't resolve this commit either in Linus's or in linux-next.
> change-id: 20241202-dp_mst_bindings-7536ffc9ae2f
>
> Best regards,
> --
> Jessica Zhang <jessica.zhang@oss.qualcomm.com>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport
2025-07-17 23:28 ` [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport Jessica Zhang
2025-07-18 9:20 ` Dmitry Baryshkov
@ 2025-07-18 9:23 ` Konrad Dybcio
2025-07-18 16:37 ` Jessica Zhang
1 sibling, 1 reply; 27+ messages in thread
From: Konrad Dybcio @ 2025-07-18 9:23 UTC (permalink / raw)
To: Jessica Zhang, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Abel Vesa,
Bjorn Andersson, Michael Turquette, Stephen Boyd, Mahadevan,
Krishna Manikandan, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Danila Tikhonov, cros-qcom-dts-watchers
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On 7/18/25 1:28 AM, Jessica Zhang wrote:
> The following chipsets support 2 total pixel streams:
> - sa8775p (on mdss_dp1)
> - sc8180x
> - sc8280xp (mdss_dp0-2 only)
> - sm8150
> - sm8350
I think 8250 can do 2 streams too, no?
sdm845/sm7150 also have the clocks for it FWIW, but that doesn't
necessarily mean they're consumed
Konrad
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport
2025-07-18 9:20 ` Dmitry Baryshkov
@ 2025-07-18 16:35 ` Jessica Zhang
0 siblings, 0 replies; 27+ messages in thread
From: Jessica Zhang @ 2025-07-18 16:35 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On 7/18/2025 2:20 AM, Dmitry Baryshkov wrote:
> On Thu, Jul 17, 2025 at 04:28:47PM -0700, Jessica Zhang wrote:
>> The following chipsets support 2 total pixel streams:
>> - sa8775p (on mdss_dp1)
>
> Uppercase chipset names.
Hi Dmitry,
Ack.
>
>> - sc8180x
>> - sc8280xp (mdss_dp0-2 only)
>> - sm8150
>> - sm8350
>
> It's very strange that SM8150 and SM8350 support MST, but SM8250
> doesn't. Are you sure? Your patch contradicts this.
Ah yes, I added the DT changes but forgot to put it in the commit msg.
>
>> - sm8450
>> - sm8650
>> - x1e80100
>>
>> The following chipset also supports 4 total pixel streams:
>> - sa8775p (mdss_dp0 only)
>>
>> Add the appropriate amount of pixel stream clocks for their respective
>
> s/amount/number/, it's countable.
Ack.
Thanks,
Jessica Zhang
>
>> displayport-controllers.
>>
>> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 ++++++++++++----
>> arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 +++--
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 +++--
>> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 +++++++---
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++++++++++-----------
>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +++--
>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +++--
>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 +++--
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 +++--
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +++--
>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +++--
>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 +++++++++-----
>> 12 files changed, 167 insertions(+), 69 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 45f536633f64..2c85eb2fc79a 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -4237,15 +4237,28 @@ mdss0_dp0: displayport-controller@af54000 {
>> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel",
>> + "stream_2_pixel",
>> + "stream_3_pixel";
>> assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
>> + assigned-clock-parents = <&mdss0_dp0_phy 0>,
>> + <&mdss0_dp0_phy 1>,
>> + <&mdss0_dp0_phy 1>,
>> + <&mdss0_dp0_phy 1>,
>> + <&mdss0_dp0_phy 1>;
>> phys = <&mdss0_dp0_phy>;
>> phy-names = "dp";
>>
>> @@ -4316,15 +4329,20 @@ mdss0_dp1: displayport-controller@af5c000 {
>> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
>> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
>> <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
>> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>> assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
>> - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
>> - assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
>> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
>> + assigned-clock-parents = <&mdss0_dp1_phy 0>,
>> + <&mdss0_dp1_phy 1>,
>> + <&mdss0_dp1_phy 1>;
>> phys = <&mdss0_dp1_phy>;
>> phy-names = "dp";
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
>> index b0e342810ae7..96090a948ade 100644
>> --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
>> @@ -2139,16 +2139,20 @@ mdss_dp0: displayport-controller@ae90000 {
>> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index b1cc3bc1aec8..48b6a17dcea0 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -5012,15 +5012,19 @@ mdss_dp: displayport-controller@ae90000 {
>> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
>> phy-names = "dp";
>> diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
>> index b84e47a461a0..ca188c7f1f26 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
>> @@ -3233,16 +3233,20 @@ mdss_dp0: displayport-controller@ae90000 {
>> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
>> @@ -3311,16 +3315,20 @@ mdss_dp1: displayport-controller@ae98000 {
>> <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> index 87555a119d94..11ea2fa0b853 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> @@ -4338,15 +4338,19 @@ mdss0_dp0: displayport-controller@ae90000 {
>> <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
>> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
>> clock-names = "core_iface", "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
>> + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
>> @@ -4417,14 +4421,18 @@ mdss0_dp1: displayport-controller@ae98000 {
>> <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
>> <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
>> <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
>> - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
>> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
>> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
>> clock-names = "core_iface", "core_aux",
>> "ctrl_link",
>> - "ctrl_link_iface", "stream_pixel";
>> + "ctrl_link_iface", "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
>> - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
>> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
>> + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
>> @@ -4494,10 +4502,12 @@ mdss0_dp2: displayport-controller@ae9a000 {
>> <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
>> <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
>> <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
>> - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
>> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
>> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
>> clock-names = "core_iface", "core_aux",
>> "ctrl_link",
>> - "ctrl_link_iface", "stream_pixel";
>> + "ctrl_link_iface", "stream_pixel",
>> + "stream_1_pixel";
>> interrupt-parent = <&mdss0>;
>> interrupts = <14>;
>> phys = <&mdss0_dp2_phy>;
>> @@ -4505,8 +4515,11 @@ mdss0_dp2: displayport-controller@ae9a000 {
>> power-domains = <&rpmhpd SC8280XP_MMCX>;
>>
>> assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
>> - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
>> - assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
>> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
>> + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
>> + assigned-clock-parents = <&mdss0_dp2_phy 0>,
>> + <&mdss0_dp2_phy 1>,
>> + <&mdss0_dp2_phy 1>;
>> operating-points-v2 = <&mdss0_dp2_opp_table>;
>>
>> #sound-dai-cells = <0>;
>> @@ -5669,10 +5682,12 @@ mdss1_dp0: displayport-controller@22090000 {
>> <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
>> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
>> clock-names = "core_iface", "core_aux",
>> "ctrl_link",
>> - "ctrl_link_iface", "stream_pixel";
>> + "ctrl_link_iface", "stream_pixel",
>> + "stream_1_pixel";
>> interrupt-parent = <&mdss1>;
>> interrupts = <12>;
>> phys = <&mdss1_dp0_phy>;
>> @@ -5680,8 +5695,11 @@ mdss1_dp0: displayport-controller@22090000 {
>> power-domains = <&rpmhpd SC8280XP_MMCX>;
>>
>> assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> - assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
>> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
>> + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
>> + assigned-clock-parents = <&mdss1_dp0_phy 0>,
>> + <&mdss1_dp0_phy 1>,
>> + <&mdss1_dp0_phy 1>;
>> operating-points-v2 = <&mdss1_dp0_opp_table>;
>>
>> #sound-dai-cells = <0>;
>> @@ -5741,10 +5759,12 @@ mdss1_dp1: displayport-controller@22098000 {
>> <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
>> <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
>> <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
>> - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
>> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
>> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
>> clock-names = "core_iface", "core_aux",
>> "ctrl_link",
>> - "ctrl_link_iface", "stream_pixel";
>> + "ctrl_link_iface", "stream_pixel",
>> + "stream_1_pixel";
>> interrupt-parent = <&mdss1>;
>> interrupts = <13>;
>> phys = <&mdss1_dp1_phy>;
>> @@ -5752,8 +5772,11 @@ mdss1_dp1: displayport-controller@22098000 {
>> power-domains = <&rpmhpd SC8280XP_MMCX>;
>>
>> assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
>> - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
>> - assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
>> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
>> + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
>> + assigned-clock-parents = <&mdss1_dp1_phy 0>,
>> + <&mdss1_dp1_phy 1>,
>> + <&mdss1_dp1_phy 1>;
>> operating-points-v2 = <&mdss1_dp1_opp_table>;
>>
>> #sound-dai-cells = <0>;
>> @@ -5813,10 +5836,12 @@ mdss1_dp2: displayport-controller@2209a000 {
>> <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
>> <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
>> <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
>> - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
>> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
>> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
>> clock-names = "core_iface", "core_aux",
>> "ctrl_link",
>> - "ctrl_link_iface", "stream_pixel";
>> + "ctrl_link_iface", "stream_pixel",
>> + "stream_1_pixel";
>> interrupt-parent = <&mdss1>;
>> interrupts = <14>;
>> phys = <&mdss1_dp2_phy>;
>> @@ -5824,8 +5849,11 @@ mdss1_dp2: displayport-controller@2209a000 {
>> power-domains = <&rpmhpd SC8280XP_MMCX>;
>>
>> assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
>> - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
>> - assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
>> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
>> + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
>> + assigned-clock-parents = <&mdss1_dp2_phy 0>,
>> + <&mdss1_dp2_phy 1>,
>> + <&mdss1_dp2_phy 1>;
>> operating-points-v2 = <&mdss1_dp2_opp_table>;
>>
>> #sound-dai-cells = <0>;
>> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> index cdb47359c4c8..3a21a2e2c04d 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> @@ -3894,16 +3894,20 @@ mdss_dp: displayport-controller@ae90000 {
>> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> index f0d18fd37aaf..fc7c610c15d2 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> @@ -4774,16 +4774,20 @@ mdss_dp: displayport-controller@ae90000 {
>> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
>> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
>> index 971c828a7555..6a930292edd3 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
>> @@ -2872,16 +2872,20 @@ mdss_dp: displayport-controller@ae90000 {
>> <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index 54c6d0fdb2af..b0680ef30c1f 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -3431,16 +3431,20 @@ mdss_dp0: displayport-controller@ae90000 {
>> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> index 71a7e3b57ece..226c457338d9 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> @@ -3545,16 +3545,20 @@ mdss_dp0: displayport-controller@ae90000 {
>> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> index 495ea9bfd008..72c63afe9029 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> @@ -5388,16 +5388,20 @@ mdss_dp0: displayport-controller@af54000 {
>> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> operating-points-v2 = <&dp_opp_table>;
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index a8eb4c5fe99f..e86b6cb20096 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -5306,16 +5306,20 @@ mdss_dp0: displayport-controller@ae90000 {
>> <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> operating-points-v2 = <&mdss_dp0_opp_table>;
>> @@ -5389,16 +5393,20 @@ mdss_dp1: displayport-controller@ae98000 {
>> <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
>> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> operating-points-v2 = <&mdss_dp1_opp_table>;
>> @@ -5472,16 +5480,20 @@ mdss_dp2: displayport-controller@ae9a000 {
>> <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
>> <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
>> - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
>> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
>> clock-names = "core_iface",
>> "core_aux",
>> "ctrl_link",
>> "ctrl_link_iface",
>> - "stream_pixel";
>> + "stream_pixel",
>> + "stream_1_pixel";
>>
>> assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
>> - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
>> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
>> assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>>
>> operating-points-v2 = <&mdss_dp2_opp_table>;
>>
>> --
>> 2.50.1
>>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport
2025-07-18 9:23 ` Konrad Dybcio
@ 2025-07-18 16:37 ` Jessica Zhang
0 siblings, 0 replies; 27+ messages in thread
From: Jessica Zhang @ 2025-07-18 16:37 UTC (permalink / raw)
To: Konrad Dybcio, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Abel Vesa,
Bjorn Andersson, Michael Turquette, Stephen Boyd, Mahadevan,
Krishna Manikandan, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Danila Tikhonov, cros-qcom-dts-watchers
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On 7/18/2025 2:23 AM, Konrad Dybcio wrote:
> On 7/18/25 1:28 AM, Jessica Zhang wrote:
>> The following chipsets support 2 total pixel streams:
>> - sa8775p (on mdss_dp1)
>> - sc8180x
>> - sc8280xp (mdss_dp0-2 only)
>> - sm8150
>> - sm8350
>
> I think 8250 can do 2 streams too, no?
Hi Konrad,
Yes, 8250 supports 2x MST. I will include it in the commit message.
Thanks,
Jessica Zhang
>
> sdm845/sm7150 also have the clocks for it FWIW, but that doesn't
> necessarily mean they're consumed
>
> Konrad
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support
2025-07-18 6:16 ` Krzysztof Kozlowski
@ 2025-07-18 16:38 ` Jessica Zhang
0 siblings, 0 replies; 27+ messages in thread
From: Jessica Zhang @ 2025-07-18 16:38 UTC (permalink / raw)
To: Krzysztof Kozlowski, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Abel Vesa,
Bjorn Andersson, Michael Turquette, Stephen Boyd, Mahadevan,
Krishna Manikandan, Konrad Dybcio, Rob Clark, Abhinav Kumar,
Danila Tikhonov, cros-qcom-dts-watchers
Cc: Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Yongxing Mou
On 7/17/2025 11:16 PM, Krzysztof Kozlowski wrote:
> On 18/07/2025 01:28, Jessica Zhang wrote:
>> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>
>> Add x1e80100 to the dp-controller bindings, fix the
>> displayport-controller reg bindings, and drop
>> assigned-clock-parents/assigned-clocks
>>
>> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
>
>
> That's not a correct tag really - drop the quotes. If this was added by
> b4, I think you might be using an older version.
Hi Krzysztof,
Thanks for the catch -- I'll upgrade b4.
BR,
Jessica Zhang
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams
2025-07-18 9:22 ` [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Dmitry Baryshkov
@ 2025-07-18 16:43 ` Jessica Zhang
0 siblings, 0 replies; 27+ messages in thread
From: Jessica Zhang @ 2025-07-18 16:43 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On 7/18/2025 2:22 AM, Dmitry Baryshkov wrote:
> On Thu, Jul 17, 2025 at 04:28:42PM -0700, Jessica Zhang wrote:
>> On some MSM chipsets, the display port controller is capable of supporting
>> up to 4 streams.
>>
>> To drive these additional streams, the pixel clocks for the corresponding
>> stream needs to be enabled.
>>
>> Fixup the documentation of some of the bindings to clarify exactly which
>> stream they correspond to, then add the new bindings and device tree
>> changes.
>>
>> ---
>> Changes in v3:
>> - Fixed dtschema errors (Rob Herring)
>> - Documented all pixel stream clocks (Dmitry)
>> - Ordered compatibility list alphabetically (Dmitry)
>> - Dropped assigned-clocks too (Dmitry)
>> - Link to v2: https://lore.kernel.org/r/20250530-dp_mst_bindings-v2-0-f925464d32a8@oss.qualcomm.com
>>
>> Changes in v2:
>> - Rebased on top of next-20250523
>> - Dropped merged maintainer patch
>> - Added a patch to make the corresponding dts change to add pixel 1
>> stream
>> - Squashed pixel 0 and pixel 1 stream binding patches (Krzysztof)
>> - Drop assigned-clock-parents bindings for dp-controller (Krzysztof)
>> - Updated dp-controller.yaml to include all chipsets that support stream
>> 1 pixel clock (Krzysztof)
>> - Added missing minItems and if statement (Krzysztof)
>> - Link to v1: https://lore.kernel.org/r/20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com
>>
>> ---
>> Abhinav Kumar (4):
>> dt-bindings: Fixup x1e80100 to add DP MST support
>> dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding
>> dt-bindings: display/msm: drop assigned-clock-parents for dp controller
>> dt-bindings: display/msm: add stream pixel clock bindings for MST
>>
>> Jessica Zhang (1):
>> arm64: dts: qcom: Add MST pixel streams for displayport
>>
>> .../bindings/display/msm/dp-controller.yaml | 53 +++++++++++-----
>> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 14 +++--
>> .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 11 ++--
>> .../bindings/display/msm/qcom,sc7180-mdss.yaml | 3 -
>> .../bindings/display/msm/qcom,sc7280-mdss.yaml | 12 ++--
>> .../bindings/display/msm/qcom,sm7150-mdss.yaml | 5 --
>> .../bindings/display/msm/qcom,sm8750-mdss.yaml | 11 ++--
>> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 21 +++----
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 +++++++---
>> arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 ++-
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++-
>> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 ++++--
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++-------
>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++-
>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 ++-
>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++-
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 ++-
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++-
>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++-
>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 ++++++---
>> include/dt-bindings/clock/qcom,dispcc-sc7280.h | 2 +
>> 21 files changed, 235 insertions(+), 133 deletions(-)
>> ---
>> base-commit: 7a88d609b069b7d2f4d10113b18fea02921bedb1
>
> Can't resolve this commit either in Linus's or in linux-next.
Ack, I'll rebase on top of the latest linux-next.
Thanks,
Jessica Zhang
>
>> change-id: 20241202-dp_mst_bindings-7536ffc9ae2f
>>
>> Best regards,
>> --
>> Jessica Zhang <jessica.zhang@oss.qualcomm.com>
>>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support
2025-07-18 9:13 ` Dmitry Baryshkov
@ 2025-07-19 0:16 ` Jessica Zhang
2025-07-19 8:42 ` Dmitry Baryshkov
0 siblings, 1 reply; 27+ messages in thread
From: Jessica Zhang @ 2025-07-19 0:16 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On 7/18/2025 2:13 AM, Dmitry Baryshkov wrote:
> On Thu, Jul 17, 2025 at 04:28:43PM -0700, Jessica Zhang wrote:
>> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> Please fix the patch subject.
Hi Dmitry,
Ack.
>
>>
>> Add x1e80100 to the dp-controller bindings, fix the
>> displayport-controller reg bindings, and drop
>> assigned-clock-parents/assigned-clocks
>
> Why?
IIRC issues with the x1e80100 dp-controller bindings (i.e. the reg
bindings) weren't being picked up by dtschema because the x1e80100-dp
compatible string wasn't in dp-controller.yaml.
I can add this to the commit msg after moving the
assigned-clocks/clock-parents change to patch 3.
>
>>
>> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
>> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/display/msm/dp-controller.yaml | 2 ++
>> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 15 +++++----------
>
> Split into two commits.
Would it be better if I kept the compatible/reg bindings fix in this
commit then squashed the assigned-clocks/clock-parents change with patch 3?
Thanks,
Jessica Zhang
>
>> 2 files changed, 7 insertions(+), 10 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
>> index 9923b065323b..4676aa8db2f4 100644
>> --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
>> @@ -29,6 +29,8 @@ properties:
>> - qcom,sdm845-dp
>> - qcom,sm8350-dp
>> - qcom,sm8650-dp
>> + - qcom,x1e80100-dp
>> +
>> - items:
>> - enum:
>> - qcom,sar2130p-dp
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
>> index 3b01a0e47333..0e699de684c8 100644
>> --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
>> @@ -170,11 +170,11 @@ examples:
>>
>> displayport-controller@ae90000 {
>> compatible = "qcom,x1e80100-dp";
>> - reg = <0 0xae90000 0 0x200>,
>> - <0 0xae90200 0 0x200>,
>> - <0 0xae90400 0 0x600>,
>> - <0 0xae91000 0 0x400>,
>> - <0 0xae91400 0 0x400>;
>> + reg = <0xae90000 0x200>,
>> + <0xae90200 0x200>,
>> + <0xae90400 0x600>,
>> + <0xae91000 0x400>,
>> + <0xae91400 0x400>;
>>
>> interrupt-parent = <&mdss>;
>> interrupts = <12>;
>> @@ -189,11 +189,6 @@ examples:
>> "ctrl_link_iface",
>> "stream_pixel";
>>
>> - assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
>> - <&dispcc_mdss_dptx0_pixel0_clk_src>;
>> - assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> - <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>> -
>> operating-points-v2 = <&mdss_dp0_opp_table>;
>>
>> power-domains = <&rpmhpd RPMHPD_MMCX>;
>>
>> --
>> 2.50.1
>>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support
2025-07-19 0:16 ` Jessica Zhang
@ 2025-07-19 8:42 ` Dmitry Baryshkov
0 siblings, 0 replies; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-07-19 8:42 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On Fri, Jul 18, 2025 at 05:16:56PM -0700, Jessica Zhang wrote:
>
>
> On 7/18/2025 2:13 AM, Dmitry Baryshkov wrote:
> > On Thu, Jul 17, 2025 at 04:28:43PM -0700, Jessica Zhang wrote:
> > > From: Abhinav Kumar <quic_abhinavk@quicinc.com>
> >
> > Please fix the patch subject.
>
> Hi Dmitry,
>
> Ack.
>
> >
> > >
> > > Add x1e80100 to the dp-controller bindings, fix the
> > > displayport-controller reg bindings, and drop
> > > assigned-clock-parents/assigned-clocks
> >
> > Why?
>
> IIRC issues with the x1e80100 dp-controller bindings (i.e. the reg bindings)
> weren't being picked up by dtschema because the x1e80100-dp compatible
> string wasn't in dp-controller.yaml.
>
> I can add this to the commit msg after moving the
> assigned-clocks/clock-parents change to patch 3.
Just explain, _why_ you are performing the change, not what is being
done (this can be understood from the patch itself).
>
> >
> > >
> > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> > > Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
> > > Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
> > > ---
> > > .../devicetree/bindings/display/msm/dp-controller.yaml | 2 ++
> > > .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 15 +++++----------
> >
> > Split into two commits.
>
> Would it be better if I kept the compatible/reg bindings fix in this commit
> then squashed the assigned-clocks/clock-parents change with patch 3?
That depends. If these chunks are required to fix warnings / errors
after adding compat string, then keep them in this patch. If not, split
them to other patches.
>
> Thanks,
>
> Jessica Zhang
>
> >
> > > 2 files changed, 7 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> > > index 9923b065323b..4676aa8db2f4 100644
> > > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> > > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> > > @@ -29,6 +29,8 @@ properties:
> > > - qcom,sdm845-dp
> > > - qcom,sm8350-dp
> > > - qcom,sm8650-dp
> > > + - qcom,x1e80100-dp
> > > +
> > > - items:
> > > - enum:
> > > - qcom,sar2130p-dp
> > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
> > > index 3b01a0e47333..0e699de684c8 100644
> > > --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
> > > +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
> > > @@ -170,11 +170,11 @@ examples:
> > > displayport-controller@ae90000 {
> > > compatible = "qcom,x1e80100-dp";
> > > - reg = <0 0xae90000 0 0x200>,
> > > - <0 0xae90200 0 0x200>,
> > > - <0 0xae90400 0 0x600>,
> > > - <0 0xae91000 0 0x400>,
> > > - <0 0xae91400 0 0x400>;
> > > + reg = <0xae90000 0x200>,
> > > + <0xae90200 0x200>,
> > > + <0xae90400 0x600>,
> > > + <0xae91000 0x400>,
> > > + <0xae91400 0x400>;
> > > interrupt-parent = <&mdss>;
> > > interrupts = <12>;
> > > @@ -189,11 +189,6 @@ examples:
> > > "ctrl_link_iface",
> > > "stream_pixel";
> > > - assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
> > > - <&dispcc_mdss_dptx0_pixel0_clk_src>;
> > > - assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> > > - <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> > > -
> > > operating-points-v2 = <&mdss_dp0_opp_table>;
> > > power-domains = <&rpmhpd RPMHPD_MMCX>;
> > >
> > > --
> > > 2.50.1
> > >
> >
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P
2025-07-17 23:28 [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Jessica Zhang
` (5 preceding siblings ...)
2025-07-18 9:22 ` [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Dmitry Baryshkov
@ 2025-07-19 9:14 ` Dmitry Baryshkov
2025-07-21 14:38 ` Rob Herring (Arm)
2025-07-28 18:29 ` Jessica Zhang
2025-07-20 0:06 ` [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Rob Herring (Arm)
7 siblings, 2 replies; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-07-19 9:14 UTC (permalink / raw)
To: Jessica Zhang
Cc: Dmitry Baryshkov, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-clk, Krzysztof Kozlowski, Yongxing Mou
On Qualcomm SA8775P and X1E80100 the DP controller might be driving
either a DisplayPort or a eDP sink (depending on the PHY that is tied to
the controller). Reflect that in the schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Jessica, your X1E8 patch also triggers warnings for several X1E8-based
laptops. Please include this patch into the series (either separately
or, better, by squashing into your first patch).
---
.../bindings/display/msm/dp-controller.yaml | 26 ++++++++++++++-----
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 4676aa8db2f4..55e37ec74591 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -176,12 +176,26 @@ allOf:
properties:
"#sound-dai-cells": false
else:
- properties:
- aux-bus: false
- reg:
- minItems: 5
- required:
- - "#sound-dai-cells"
+ if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-dp
+ - qcom,x1e80100-dp
+ then:
+ oneOf:
+ - required:
+ - aux-bus
+ - required:
+ - "#sound-dai-cells"
+ else:
+ properties:
+ aux-bus: false
+ reg:
+ minItems: 5
+ required:
+ - "#sound-dai-cells"
additionalProperties: false
--
2.39.5
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams
2025-07-17 23:28 [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Jessica Zhang
` (6 preceding siblings ...)
2025-07-19 9:14 ` [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P Dmitry Baryshkov
@ 2025-07-20 0:06 ` Rob Herring (Arm)
7 siblings, 0 replies; 27+ messages in thread
From: Rob Herring (Arm) @ 2025-07-20 0:06 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, cros-qcom-dts-watchers, linux-arm-msm,
Bjorn Andersson, Sean Paul, freedreno, Krishna Manikandan,
Krzysztof Kozlowski, Conor Dooley, Abel Vesa, Yongxing Mou,
Danila Tikhonov, Kuogee Hsieh, Maxime Ripard, David Airlie,
dri-devel, Krzysztof Kozlowski, Maarten Lankhorst, Stephen Boyd,
Dmitry Baryshkov, Abhinav Kumar, Abhinav Kumar, linux-kernel,
Marijn Suijten, linux-clk, Rob Clark, Michael Turquette,
Thomas Zimmermann, Mahadevan, Simona Vetter, Konrad Dybcio,
devicetree
On Thu, 17 Jul 2025 16:28:42 -0700, Jessica Zhang wrote:
> On some MSM chipsets, the display port controller is capable of supporting
> up to 4 streams.
>
> To drive these additional streams, the pixel clocks for the corresponding
> stream needs to be enabled.
>
> Fixup the documentation of some of the bindings to clarify exactly which
> stream they correspond to, then add the new bindings and device tree
> changes.
>
> ---
> Changes in v3:
> - Fixed dtschema errors (Rob Herring)
> - Documented all pixel stream clocks (Dmitry)
> - Ordered compatibility list alphabetically (Dmitry)
> - Dropped assigned-clocks too (Dmitry)
> - Link to v2: https://lore.kernel.org/r/20250530-dp_mst_bindings-v2-0-f925464d32a8@oss.qualcomm.com
>
> Changes in v2:
> - Rebased on top of next-20250523
> - Dropped merged maintainer patch
> - Added a patch to make the corresponding dts change to add pixel 1
> stream
> - Squashed pixel 0 and pixel 1 stream binding patches (Krzysztof)
> - Drop assigned-clock-parents bindings for dp-controller (Krzysztof)
> - Updated dp-controller.yaml to include all chipsets that support stream
> 1 pixel clock (Krzysztof)
> - Added missing minItems and if statement (Krzysztof)
> - Link to v1: https://lore.kernel.org/r/20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com
>
> ---
> Abhinav Kumar (4):
> dt-bindings: Fixup x1e80100 to add DP MST support
> dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding
> dt-bindings: display/msm: drop assigned-clock-parents for dp controller
> dt-bindings: display/msm: add stream pixel clock bindings for MST
>
> Jessica Zhang (1):
> arm64: dts: qcom: Add MST pixel streams for displayport
>
> .../bindings/display/msm/dp-controller.yaml | 53 +++++++++++-----
> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 14 +++--
> .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 11 ++--
> .../bindings/display/msm/qcom,sc7180-mdss.yaml | 3 -
> .../bindings/display/msm/qcom,sc7280-mdss.yaml | 12 ++--
> .../bindings/display/msm/qcom,sm7150-mdss.yaml | 5 --
> .../bindings/display/msm/qcom,sm8750-mdss.yaml | 11 ++--
> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 21 +++----
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 +++++++---
> arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 ++++--
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++-------
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++-
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 ++++++---
> include/dt-bindings/clock/qcom,dispcc-sc7280.h | 2 +
> 21 files changed, 235 insertions(+), 133 deletions(-)
> ---
> base-commit: 7a88d609b069b7d2f4d10113b18fea02921bedb1
> change-id: 20241202-dp_mst_bindings-7536ffc9ae2f
>
> Best regards,
> --
> Jessica Zhang <jessica.zhang@oss.qualcomm.com>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: base-commit 7a88d609b069b7d2f4d10113b18fea02921bedb1 not known, ignoring
Base: attempting to guess base-commit...
Base: tags/v6.16-rc2-698-g6b93840116df (exact match)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com:
arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['edp-panel'], 'enable-gpios': [[71, 74, 0]], 'power-supply': [[258]], 'pinctrl-0': [[259]], 'pinctrl-names': ['default'], 'port': {'endpoint': {'remote-endpoint': [[260]], 'phandle': 257}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['edp-panel'], 'power-supply': [[276]], 'phandle': 597, 'port': {'endpoint': {'remote-endpoint': [[277]], 'phandle': 275}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['samsung,atna45dc02', 'samsung,atna33xc20'], 'enable-gpios': [[275, 4, 0]], 'power-supply': [[276]], 'pinctrl-0': [[277]], 'pinctrl-names': ['default'], 'port': {'endpoint': {'remote-endpoint': [[278]], 'phandle': 274}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1p42100-crd.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['samsung,atna45af01', 'samsung,atna33xc20'], 'enable-gpios': [[268, 4, 0]], 'power-supply': [[269]], 'pinctrl-0': [[270]], 'pinctrl-names': ['default'], 'port': {'endpoint': {'remote-endpoint': [[271]], 'phandle': 267}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1p42100-crd.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['edp-panel'], 'power-supply': [[272]], 'backlight': [[273]], 'port': {'endpoint': {'remote-endpoint': [[274]], 'phandle': 271}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['edp-panel'], 'power-supply': [[268]], 'port': {'endpoint': {'remote-endpoint': [[269]], 'phandle': 267}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['samsung,atna56ac03', 'samsung,atna33xc20'], 'enable-gpios': [[261, 4, 0]], 'power-supply': [[262]], 'pinctrl-0': [[263]], 'pinctrl-names': ['default'], 'port': {'endpoint': {'remote-endpoint': [[264]], 'phandle': 260}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['edp-panel'], 'power-supply': [[276]], 'backlight': [[277]], 'phandle': 603, 'port': {'endpoint': {'remote-endpoint': [[278]], 'phandle': 275}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-hp-elitebook-ultra-g1q.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['edp-panel'], 'power-supply': [[272]], 'backlight': [[273]], 'port': {'endpoint': {'remote-endpoint': [[274]], 'phandle': 271}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-hp-elitebook-ultra-g1q.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus15.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['edp-panel'], 'backlight': [[266]], 'power-supply': [[267]], 'port': {'endpoint': {'remote-endpoint': [[268]], 'phandle': 265}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus15.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['samsung,atna45af01', 'samsung,atna33xc20'], 'enable-gpios': [[278, 4, 0]], 'power-supply': [[279]], 'pinctrl-0': [[280]], 'pinctrl-names': ['default'], 'port': {'endpoint': {'remote-endpoint': [[281]], 'phandle': 277}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus13.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): aux-bus: False schema does not allow {'panel': {'compatible': ['edp-panel'], 'backlight': [[266]], 'power-supply': [[267]], 'port': {'endpoint': {'remote-endpoint': [[268]], 'phandle': 265}}}}
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus13.dtb: displayport-controller@aea0000 (qcom,x1e80100-dp): '#sound-dai-cells' is a required property
from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P
2025-07-19 9:14 ` [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P Dmitry Baryshkov
@ 2025-07-21 14:38 ` Rob Herring (Arm)
2025-07-28 18:29 ` Jessica Zhang
1 sibling, 0 replies; 27+ messages in thread
From: Rob Herring (Arm) @ 2025-07-21 14:38 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Yongxing Mou, Mahadevan, Simona Vetter, Sean Paul, Abel Vesa,
Dmitry Baryshkov, freedreno, Michael Turquette,
cros-qcom-dts-watchers, Danila Tikhonov, David Airlie,
linux-arm-msm, Bjorn Andersson, Conor Dooley, Krzysztof Kozlowski,
linux-kernel, Kuogee Hsieh, Rob Clark, Krishna Manikandan,
Thomas Zimmermann, dri-devel, Krzysztof Kozlowski, devicetree,
Konrad Dybcio, Maarten Lankhorst, Marijn Suijten, Abhinav Kumar,
linux-clk, Maxime Ripard, Jessica Zhang, Stephen Boyd
On Sat, 19 Jul 2025 12:14:45 +0300, Dmitry Baryshkov wrote:
>
> On Qualcomm SA8775P and X1E80100 the DP controller might be driving
> either a DisplayPort or a eDP sink (depending on the PHY that is tied to
> the controller). Reflect that in the schema.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>
> Jessica, your X1E8 patch also triggers warnings for several X1E8-based
> laptops. Please include this patch into the series (either separately
> or, better, by squashing into your first patch).
>
> ---
> .../bindings/display/msm/dp-controller.yaml | 26 ++++++++++++++-----
> 1 file changed, 20 insertions(+), 6 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST
2025-07-17 23:28 ` [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST Jessica Zhang
` (2 preceding siblings ...)
2025-07-18 9:16 ` Dmitry Baryshkov
@ 2025-07-24 11:55 ` Dmitry Baryshkov
3 siblings, 0 replies; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-07-24 11:55 UTC (permalink / raw)
To: Jessica Zhang
Cc: Abhinav Kumar, Dmitry Baryshkov, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
Abhinav Kumar, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, linux-clk, Krzysztof Kozlowski, Yongxing Mou
On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote:
> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>
> On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more,
> the display port controller can support more than one pixel stream
> (multi-stream transport).
>
> These chipsets can support up to 4 stream pixel clocks for display port
> controller. To support MST on these platforms, add the appropriate
> stream pixel clock bindings
>
> Since this mode is not supported on all chipsets, add exception
> rules and min/max items to clearly mark which chipsets support
> only SST mode (single stream) and which ones support MST.
>
> Note: On chipsets that do support MST, the number of streams supported
> can vary between controllers. For example, SA8775P supports 4 MST
> streams on mdss_dp0 but only 2 streams on mdss_dp1.
>
> In addition, many chipsets depend on the "sm8350-dp" compatibility
> string but not all (ex. SM6350) support MST. Because of these reasons,
> the min/maxItem for MST-supported platforms is a range of 5-8.
>
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
> ---
> .../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++-
> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++--
> .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++--
> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++--
> 6 files changed, 59 insertions(+), 11 deletions(-)
I've cross-checked. We need to stop declaring SM6350 as compatible with
SM8350, it doesn't provide MST support (and so there will be a need for
a driver update too). Other than that, please document DP MST on SDM845.
With those changes in place, I think, all platforms will be covered.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P
2025-07-19 9:14 ` [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P Dmitry Baryshkov
2025-07-21 14:38 ` Rob Herring (Arm)
@ 2025-07-28 18:29 ` Jessica Zhang
2025-07-28 18:59 ` Dmitry Baryshkov
1 sibling, 1 reply; 27+ messages in thread
From: Jessica Zhang @ 2025-07-28 18:29 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Dmitry Baryshkov, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-clk, Krzysztof Kozlowski, Yongxing Mou
On 7/19/2025 2:14 AM, Dmitry Baryshkov wrote:
>
> On Qualcomm SA8775P and X1E80100 the DP controller might be driving
> either a DisplayPort or a eDP sink (depending on the PHY that is tied to
> the controller). Reflect that in the schema.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>
> Jessica, your X1E8 patch also triggers warnings for several X1E8-based
> laptops. Please include this patch into the series (either separately
> or, better, by squashing into your first patch).
Hey Dmitry,
Thanks for providing this patch -- I'll squash this with patch 1 and add
your signed-off-by w/note.
Thanks,
Jessica Zhang
>
> ---
> .../bindings/display/msm/dp-controller.yaml | 26 ++++++++++++++-----
> 1 file changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> index 4676aa8db2f4..55e37ec74591 100644
> --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> @@ -176,12 +176,26 @@ allOf:
> properties:
> "#sound-dai-cells": false
> else:
> - properties:
> - aux-bus: false
> - reg:
> - minItems: 5
> - required:
> - - "#sound-dai-cells"
> + if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sa8775p-dp
> + - qcom,x1e80100-dp
> + then:
> + oneOf:
> + - required:
> + - aux-bus
> + - required:
> + - "#sound-dai-cells"
> + else:
> + properties:
> + aux-bus: false
> + reg:
> + minItems: 5
> + required:
> + - "#sound-dai-cells"
>
> additionalProperties: false
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P
2025-07-28 18:29 ` Jessica Zhang
@ 2025-07-28 18:59 ` Dmitry Baryshkov
0 siblings, 0 replies; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-07-28 18:59 UTC (permalink / raw)
To: Jessica Zhang
Cc: Dmitry Baryshkov, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kuogee Hsieh, Abel Vesa, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Mahadevan, Krishna Manikandan, Konrad Dybcio,
Rob Clark, Abhinav Kumar, Danila Tikhonov, cros-qcom-dts-watchers,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-clk, Krzysztof Kozlowski, Yongxing Mou
On Mon, Jul 28, 2025 at 11:29:31AM -0700, Jessica Zhang wrote:
>
>
> On 7/19/2025 2:14 AM, Dmitry Baryshkov wrote:
> >
> > On Qualcomm SA8775P and X1E80100 the DP controller might be driving
> > either a DisplayPort or a eDP sink (depending on the PHY that is tied to
> > the controller). Reflect that in the schema.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> >
> > Jessica, your X1E8 patch also triggers warnings for several X1E8-based
> > laptops. Please include this patch into the series (either separately
> > or, better, by squashing into your first patch).
>
> Hey Dmitry,
>
> Thanks for providing this patch -- I'll squash this with patch 1 and add
> your signed-off-by w/note.
Perfect! Then it should be S-o-B and Co-developed-by. Thank you!
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2025-07-28 18:59 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-07-17 23:28 [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Jessica Zhang
2025-07-17 23:28 ` [PATCH v3 1/5] dt-bindings: Fixup x1e80100 to add DP MST support Jessica Zhang
2025-07-18 6:16 ` Krzysztof Kozlowski
2025-07-18 16:38 ` Jessica Zhang
2025-07-18 9:13 ` Dmitry Baryshkov
2025-07-19 0:16 ` Jessica Zhang
2025-07-19 8:42 ` Dmitry Baryshkov
2025-07-17 23:28 ` [PATCH v3 2/5] dt-bindings: clock: Add SC7280 DISPCC DP pixel 1 clock binding Jessica Zhang
2025-07-17 23:28 ` [PATCH v3 3/5] dt-bindings: display/msm: drop assigned-clock-parents for dp controller Jessica Zhang
2025-07-18 7:32 ` Krzysztof Kozlowski
2025-07-17 23:28 ` [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST Jessica Zhang
2025-07-18 7:26 ` Krzysztof Kozlowski
2025-07-18 9:14 ` Dmitry Baryshkov
2025-07-18 9:16 ` Dmitry Baryshkov
2025-07-24 11:55 ` Dmitry Baryshkov
2025-07-17 23:28 ` [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for displayport Jessica Zhang
2025-07-18 9:20 ` Dmitry Baryshkov
2025-07-18 16:35 ` Jessica Zhang
2025-07-18 9:23 ` Konrad Dybcio
2025-07-18 16:37 ` Jessica Zhang
2025-07-18 9:22 ` [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Dmitry Baryshkov
2025-07-18 16:43 ` Jessica Zhang
2025-07-19 9:14 ` [PATCH] dt-bindings: display/msm: dp-controller: allow eDP for X1E8 and SA8775P Dmitry Baryshkov
2025-07-21 14:38 ` Rob Herring (Arm)
2025-07-28 18:29 ` Jessica Zhang
2025-07-28 18:59 ` Dmitry Baryshkov
2025-07-20 0:06 ` [PATCH v3 0/5] dt-bindings: msm/dp: Add support for 4 pixel streams Rob Herring (Arm)
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