From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id ; Wed, 20 Jun 2001 15:00:18 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id ; Wed, 20 Jun 2001 15:00:08 -0400 Received: from pixie.isr.ist.utl.pt ([193.136.138.97]:53520 "EHLO pixie.isr.ist.utl.pt") by vger.kernel.org with ESMTP id ; Wed, 20 Jun 2001 15:00:02 -0400 To: linux-kernel@vger.kernel.org Subject: Re: Threads FAQ entry incomplete In-Reply-To: <20010620104800.D1174@w-mikek2.des.beaverton.ibm.com> Mime-Version: 1.0 (generated by tm-edit 7.108) Content-Type: text/plain; charset=US-ASCII From: Rodrigo Ventura Date: 20 Jun 2001 19:59:29 +0100 In-Reply-To: Mike Kravetz's message of "Wed, 20 Jun 2001 10:48:00 -0700" Message-ID: X-Mailer: Gnus v5.6.45/XEmacs 21.1 - "Biscayne" Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org >>>>> "Mike" == Mike Kravetz writes: Mike> Note that in the 2 and 4 CPU cases, the run queue length is Mike> aprox 2x the number of CPUs and the scheduler seems to Mike> perform reasonably well with respect to locking. In the 8 Mike> CPU case, the number of tasks is aprox equal to the number Mike> of CPUs yet scheduler performance has gone downhill. Obviously, since as the number of CPUs grow, you begin experiencing the bottleneck of shared resources (bus, memory, I/O, etc.) multiplexing. For a large number of processors, the performance becomes very far from linear, i.e. the gain obtained from an extra CPU becomes very minute. That's why massively parallel computers tend to use separate motherboards for each CPU. BTW, I have a question: Can the availability of dual-CPU boards for intel and amd processors, rather then tri- or quadra-CPU boards, be explained with the fact that the performance degrades significantly for three or more CPUs? Or is there a technological and/or comercial reason behind? I heard somewhere that the intel holds some patents related with many-CPU boards... Cheers, -- *** Rodrigo Martins de Matos Ventura *** Web page: http://www.isr.ist.utl.pt/~yoda *** Teaching Assistant and PhD Student at ISR: *** Instituto de Sistemas e Robotica, Polo de Lisboa *** Instituto Superior Tecnico, Lisboa, PORTUGAL *** PGP fingerprint = 0119 AD13 9EEE 264A 3F10 31D3 89B3 C6C4 60C6 4585