Re: [PATCH] perf, x86: Add Sandy Bridge constraints for CYCLE_ACTIVITY.*

[Andi Kleen <andi@firstfloor.org>]

Andi Kleen <andi@firstfloor.org> writes:

> From: Andi Kleen <ak@linux.intel.com>

Ping! Patch is missing review.

-Andi

>
> Add CYCLE_ACTIVITY.CYCLES_NO_DISPATCH/CYCLES_L1D_PENDING
> These recently documented events have restrictions to counter 0-3
> and counter 2 respectively.  The scheduler needs to know that
> to schedule them correctly.
>
> IvyBridge already has the necessary constraints.
>
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> ---
>  arch/x86/kernel/cpu/perf_event_intel.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 5b59c6c..0d2f9d8 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -104,6 +104,8 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
>  	INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
>  	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
>  	INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
> +	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
> +	INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
>  	EVENT_CONSTRAINT_END
>  };

-- 
ak@linux.intel.com -- Speaking for myself only