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From: Andi Kleen <andi@firstfloor.org>
To: "Yu\, Fenghua" <fenghua.yu@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@elte.hu>,
        H Peter Anvin <hpa@zytor.com>, "Luck\, Tony" <tony.luck@intel.com>,
        "Mallick\, Asit K" <asit.k.mallick@intel.com>,
        "Siddha\, Suresh B" <suresh.b.siddha@intel.com>,
        Len Brown <lenb@kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>, alan@lxorguk.ukuu.org.uk
Subject: Re: [PATCH 1/8] x86, apic.c: Disable irq0 if CPU enables ARAT for local apic timer
References: <1317832759-10223-1-git-send-email-fenghua.yu@intel.com>
	<1317832759-10223-2-git-send-email-fenghua.yu@intel.com>
	<alpine.LFD.2.02.1110052045430.18778@ionos>
	<493994B35A117E4F832F97C4719C4C040136F7CBF3@orsmsx505.amr.corp.intel.com>
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Date: Wed, 05 Oct 2011 19:43:24 -0700
In-Reply-To: <493994B35A117E4F832F97C4719C4C040136F7CC8E@orsmsx505.amr.corp.intel.com>
	(Fenghua Yu's message of "Wed, 5 Oct 2011 13:11:46 -0700")
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"Yu, Fenghua" <fenghua.yu@intel.com> writes:
>
> SC1200 WDT DRIVER
> M:      Zwane Mwaikambo <zwane@arm.linux.org.uk>
> S:      Maintained
> F:      drivers/watchdog/sc1200wdt.c
>
> I was hoping Zwane knows which PCI quirks depends on CPU0.

At least one AMD SIS chipset relied on IRQ0 always being on CPU0 
Not sure we got a quirk for it because the existing code handled it
(I guess it's reasonable to just blacklist for all of SIS,
i don't think they ever did anything multi-socket)
Alan may remember more.

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only