From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758971Ab2EYWtH (ORCPT ); Fri, 25 May 2012 18:49:07 -0400 Received: from mga03.intel.com ([143.182.124.21]:19368 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755237Ab2EYWtF (ORCPT ); Fri, 25 May 2012 18:49:05 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="104453223" From: Andi Kleen To: Stephane Eranian Cc: David Ahern , Peter Zijlstra , LKML , Gleb Natapov , Avi Kivity Subject: Re: perf, x86: only do lbr init if bts is available References: <4FBE5FA6.5050802@gmail.com> <4FBE64D0.7040507@gmail.com> Date: Fri, 25 May 2012 15:49:04 -0700 In-Reply-To: (Stephane Eranian's message of "Thu, 24 May 2012 19:11:28 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Stephane Eranian writes: > On Thu, May 24, 2012 at 6:41 PM, David Ahern wrote: >> On 5/24/12 10:35 AM, Stephane Eranian wrote: >>> >>> Well, no. There is no connection between BTS and LBR and you're creating >>> one. >> >> >> Ok. That was not clear to me from skimming the manual. >> Then should it be tied to X86_FEATURE_DTES64? >> > No, it is unrelated to the Debug Store. > There is really nothing you can use to figure that out, not event IA32_DEBUGCTL. One way to do it would be to reread DEBUGCTL after writing and see if the bit really changed to 1. If not assume LBR is not available. -Andi -- ak@linux.intel.com -- Speaking for myself only