Re: MMCONFIG violates pci power mgmt spec

[Andi Kleen <ak@muc.de>]

"Michael Chan" <mchan@broadcom.com> writes:

> For example, if the device is transitioning into or out of D3hot, the
> spec requires a delay of 10 msec before any accesses can be made to the
> device. The dummy read in pci_mmcfg_write violates the delay
> requirements even though pci_set_power_state has all the necessary
> delays.

Interesting. What happens? Hangs? 

>
> I have contacted "Durairaj, Sundarapandian
> <sundarapandian.durairaj@intel.com>" but did not get a response, and so
> I'm posting to this list. One question I wanted to ask him was whether
> the dummy read was necessary. If the Intel chipset treats the mmconfig
> write as a non-posted write, the dummy read becomes unnecessary and
> removing it will solve the problem. If it is treated as a posted write,

This was added to keep the new access method to be as compatible
as possible to the old method (which never posts). 

If someone cites the spec that says that it is not allowed I guess
it could be removed.

In the worst case we could add a new pci_read_config_*_relaxed() 
or somesuch.

> I wonder if there is another way to flush it other than reading from the
> target device.

Reading is the official way to flush.

-Andi