Re: FYI: i.MX8MP ISP (RKISP1) MI registers corruption: resolved

Krzysztof Hałasa
2025-08-12T12:28:10Z

Hi Laurent,

>> - anyway, lowering the frequencies of ISP and MEDIA root clocks fixes
>> the ISP2 MI corruption. I'm currently investigating PMIC settings
>> (both my Compulab and SolidRun modules use PCA9450C PMICs), so perhaps
>> I'll be able to use the higher 500 MHz clocks. It doesn't matter much,
>> though.

Well, apparently my Compulab UCM module provides overdrive power. At
least the PMIC driver says so (in /sys pseudofiles). I guess SolidRun
won't be different.

1. At least two different designs are affected (Compulab and SolidRun),
2. the PCA9450C is THE i.MX8MP PMIC, most probably connected to the CPU
exactly as in the datasheet (at least WRT VDD_SOC power lines),
3. NXP people experienced the problem on their (which ones?) boards, too

Well... They specify (IMX8MPIEC = the datasheet):

"Two instances of 4-lane MIPI CSI interface and HDR ISP
• For single Camera, MIPI CSI 1 can support up to 400/500 MHz pixel
clock in the Nominal/Overdrive mode.
• For single Camera, MIPI CSI 2 can support up to 277 MHz pixel clock.
• For dual Camera, both MIPI CSI can support up to 266 MHz pixel clock.
• 2x ISP supporting 375 Mpixel/s aggregate performance and up to
3-exposure HDR processing.
•When one camera is used, support up to 12MP@30fps or 4kp45
•When two cameras are used, each supports up to 1080p80"

So, while ISP clock is not exactly pixel clock, perhaps they mean that
the ISP clock is to be limited as well.

ISP2 at 400 MHz (single camera) works for me (with a 1080p60 12-bit
IMX462 sensor), but I haven't tested in extreme conditions etc.

> I think it would make sense to lower the default clock frequencies, and
> provide an overlay to enable overdrive mode.
>
> It's also interesting that the issue only affected the second ISP, as
> the first one should also be limited to 400 MHz in normal mode.

Right. Maybe it's not the overdrive mode after all. I will do more tests
soon.