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To: "Martin J. Bligh" <mbligh@aracnet.com>
cc: linux-kernel@vger.kernel.org, jun.nakajima@intel.com
Subject: Re: CONFIG_IRQBALANCE for AMD64?
References: <20Uhn-7bP-11@gated-at.bofh.it> <20UqZ-7i7-5@gated-at.bofh.it>
From: Andi Kleen <ak@muc.de>
Date: Fri, 28 May 2004 23:45:11 +0200
In-Reply-To: <20UqZ-7i7-5@gated-at.bofh.it> (Martin J. Bligh's message of
 "Fri, 28 May 2004 20:40:09 +0200")
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"Martin J. Bligh" <mbligh@aracnet.com> writes:

> Whatever we do ... all arches are going to need to provide a way to direct
> interrupts to a certain CPU, or group thereof. Can they all do that already?
> I'll confess to not having looked at non-i386 arches. And are others as
> brain damaged as the P4? or do they do something round-robin by default?

I wouldn't really blame the the P4, it's the IO-APICs in the chipsets
that balance or not balance.

At least the AMD chipsets found in most Opteron boxes need software 
balancing too.

-Andi