Re: [PATCH 1/2] mtd: spi-nor: winbond: Add support for w25q01jv

[Pratyush Yadav <pratyush@kernel.org>]

On Wed, Jan 15 2025, Miquel Raynal wrote:

> Hello Pratyush,
>
>> Okay, I am confused because you said earlier that:
>>
>>> The bug that has been experienced followed this sequence:
>>> - send the write enable command (non-volatile)
>>> - wait for the ready/busy bit, ie. wait for the WEL bit to be set
>>>   because it is non-volatile write
>>> - active die is ready, (but idle die is not!)
>>> - enter 4-byte address mode, only the die that is ready processes the
>>>   command.
>>
>> Which says the WEL bit being set itself is racy. What I understand from
>> that is one die is ready to take writes and the other is not. Now when
>> you try to write the SR to enable 4B mode, it would only work on the die
>> that got the WEL set. The other one ignores it and stays in 3B mode. Do
>> I understand this correctly? To fix this you need to wait after the
>> write enable, before you initiate the write SR operation.
>
> Actually I think you're right. The thing is, Winbond WEL bit are
> non-volatile by default, whereas you were assuming it would be. Maybe
> the proper fix is to do both?
> - Using the volatile 'write enable'
> and
> - Making sure we wait after the (other) commands tampering with all dies.

Yeah. You can do that or you can do the wait after sending the write
enable. Either case would need you to implement a custom write enable
function for the chip so from the code perspective, it should be about
the same. Though I do think using the volatile write enable seems to be
faster and easier to reason about.

-- 
Regards,
Pratyush Yadav