From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A5F924A7CC for ; Wed, 15 Jan 2025 20:05:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736971522; cv=none; b=UHx51Wj6gH7jtZ6sNwMyCxIE1WRKe8TZ3i/6auoqNXaQFqDH+FlOL3wGSUlHG0vQUzAmpUa+bV4959tobpcWf3X2pbHTJEOnOjxNCeFbKOmwZKxZHaZejwG7hAtQm0W9HU6i28Cwptc3QFIB3riZPFTB8mdFFhtoculYLmlZKj4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736971522; c=relaxed/simple; bh=qqfEuTjFBBI+9p04Q1SHZHZjZMbwfzV9BqTMfmjJkm4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=Q1bpwbOQfKWyO6bZ/mL5807TXaGd98vVWCSnSxmtB82dW6Rtn8c7p6FFIzsC0aLhbNSKojHoe8uRPwaH/YG/CIZNVh/h/aIrba/N3OGRWilnlL0pVmI3MzNzlkG/RFpLrQUYwogeJUfz7DXyt1o7oS71x/tRfkfvymHGAjTY69M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ol/KOJEN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ol/KOJEN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 76A16C4CED1; Wed, 15 Jan 2025 20:05:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736971521; bh=qqfEuTjFBBI+9p04Q1SHZHZjZMbwfzV9BqTMfmjJkm4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=ol/KOJENApeGimw/wu9z0hfoesCdH82/8+b2I4Bhw/CyUC/23Nn2huskbx2KwfAgi UoHXzXzxb87LhgK74Snf/xfGZqM1iWILT2R0lYs5q8ZRJVoGgU3zCQis23zqYZboSw hpcYOjkbYrSaQoW0JgowcrAHBlLnfMGNRrZEH8chxDe/b9ipm3GJrcA8pnRP4ZNdlC uN15OTYHwesL2V/GjCRtWlixN35XQisRGWdZWaY9Tui5oxmfzsBSabs+mFMLjYMt/P LsIXPEZYG+5AUFdpr1QkJkT/wbZKx6rWaKRa8d51Sb4aUzjN2iistloqCbbnWy16f0 Zoi5oNfvNaglw== From: Pratyush Yadav To: Miquel Raynal Cc: Pratyush Yadav , Tudor Ambarus , Michael Walle , Richard Weinberger , Vignesh Raghavendra , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] mtd: spi-nor: winbond: Add support for w25q01jv In-Reply-To: <87zfjrlwpc.fsf@bootlin.com> (Miquel Raynal's message of "Wed, 15 Jan 2025 20:10:39 +0100") References: <20241224-winbond-6-12-rc1-nor-volatile-bit-v1-0-f7c4dff66182@bootlin.com> <20241224-winbond-6-12-rc1-nor-volatile-bit-v1-1-f7c4dff66182@bootlin.com> <871pxp798c.fsf@bootlin.com> <87a5btslfl.fsf@bootlin.com> <87zfjrlwpc.fsf@bootlin.com> Date: Wed, 15 Jan 2025 20:05:19 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Wed, Jan 15 2025, Miquel Raynal wrote: > Hello Pratyush, > >> Okay, I am confused because you said earlier that: >> >>> The bug that has been experienced followed this sequence: >>> - send the write enable command (non-volatile) >>> - wait for the ready/busy bit, ie. wait for the WEL bit to be set >>> because it is non-volatile write >>> - active die is ready, (but idle die is not!) >>> - enter 4-byte address mode, only the die that is ready processes the >>> command. >> >> Which says the WEL bit being set itself is racy. What I understand from >> that is one die is ready to take writes and the other is not. Now when >> you try to write the SR to enable 4B mode, it would only work on the die >> that got the WEL set. The other one ignores it and stays in 3B mode. Do >> I understand this correctly? To fix this you need to wait after the >> write enable, before you initiate the write SR operation. > > Actually I think you're right. The thing is, Winbond WEL bit are > non-volatile by default, whereas you were assuming it would be. Maybe > the proper fix is to do both? > - Using the volatile 'write enable' > and > - Making sure we wait after the (other) commands tampering with all dies. Yeah. You can do that or you can do the wait after sending the write enable. Either case would need you to implement a custom write enable function for the chip so from the code perspective, it should be about the same. Though I do think using the volatile write enable seems to be faster and easier to reason about. -- Regards, Pratyush Yadav