Re: [PATCH v1 3/6] mtd: spi-nor: get rid of SPI_NOR_NO_FR

Pratyush Yadav
2024-04-17T13:39:19Z

Hi Michael,

On Fri, Apr 12 2024, Michael Walle wrote:

> The evervision FRAM devices are the only user of the NO_FR flag. Drop
> the global flag and instead use a manufacturer fixup for the evervision
> flashes to drop the fast read support.
>
> Signed-off-by: Michael Walle <mwalle@kernel.org>
> ---
> Please note, that the fast read opcode will still be set in
> spi_nor_init_default_params(), but the selection of the read opcodes
> just depends on the mask.

Since that is the case now, might as well drop the

if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)

in spi_nor_init_default_params().

>
> That is also something I want to fix soon: the opcodes can always
> be set and the drivers/SFDP will only set the mask. Opcodes then can be
> switched between 3b and 4b ones if necessary.
> ---
> drivers/mtd/spi-nor/core.c | 12 +++++-------
> drivers/mtd/spi-nor/core.h | 2 --
> drivers/mtd/spi-nor/everspin.c | 19 +++++++++++++++----
> 3 files changed, 20 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index fb76e0522665..65e6531ada0a 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2952,14 +2952,12 @@ static void spi_nor_init_default_params(struct spi_nor *nor)
> params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE;
> params->n_banks = info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS;
>
> - if (!(info->flags & SPI_NOR_NO_FR)) {
> - /* Default to Fast Read for DT and non-DT platform devices. */
> - params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
> + /* Default to Fast Read for DT and non-DT platform devices. */
> + params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
>
> - /* Mask out Fast Read if not requested at DT instantiation. */
> - if (np && !of_property_read_bool(np, "m25p,fast-read"))
> - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
> - }
> + /* Mask out Fast Read if not requested at DT instantiation. */
> + if (np && !of_property_read_bool(np, "m25p,fast-read"))
> + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;

Nit: move this above where SNOR_CMD_READ_FAST is set up.

Also, I think this is a bit clearer:

/* Default to Fast Read for non-DT and enable it if requested by DT. */
if (!np || of_property_read_bool(np, "m25p,fast-read"))
params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;

>
> /* (Fast) Read settings. */
> params->hwcaps.mask |= SNOR_HWCAPS_READ;
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 072c69b0d06c..9aa7d6399c8a 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -479,7 +479,6 @@ struct spi_nor_id {
> * Usually these will power-up in a write-protected
> * state.
> * SPI_NOR_NO_ERASE: no erase command needed.
> - * SPI_NOR_NO_FR: can't do fastread.
> * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.
> * SPI_NOR_RWW: flash supports reads while write.
> *
> @@ -528,7 +527,6 @@ struct flash_info {
> #define SPI_NOR_BP3_SR_BIT6 BIT(4)
> #define SPI_NOR_SWP_IS_VOLATILE BIT(5)
> #define SPI_NOR_NO_ERASE BIT(6)
> -#define SPI_NOR_NO_FR BIT(7)
> #define SPI_NOR_QUAD_PP BIT(8)
> #define SPI_NOR_RWW BIT(9)

Move the other bits up since the slot is now free.

>
> diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
> index 5f321e24ae7d..0720a61947e7 100644
> --- a/drivers/mtd/spi-nor/everspin.c
> +++ b/drivers/mtd/spi-nor/everspin.c
> @@ -14,28 +14,39 @@ static const struct flash_info everspin_nor_parts[] = {
> .size = SZ_16K,
> .sector_size = SZ_16K,
> .addr_nbytes = 2,
> - .flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
> + .flags = SPI_NOR_NO_ERASE,
> }, {
> .name = "mr25h256",
> .size = SZ_32K,
> .sector_size = SZ_32K,
> .addr_nbytes = 2,
> - .flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
> + .flags = SPI_NOR_NO_ERASE,
> }, {
> .name = "mr25h10",
> .size = SZ_128K,
> .sector_size = SZ_128K,
> - .flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
> + .flags = SPI_NOR_NO_ERASE,
> }, {
> .name = "mr25h40",
> .size = SZ_512K,
> .sector_size = SZ_512K,
> - .flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,
> + .flags = SPI_NOR_NO_ERASE,
> }
> };
>
> +static void evervision_nor_default_init(struct spi_nor *nor)
> +{
> + /* Everspin FRAMs don't support the fast read opcode. */
> + nor->params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
> +}
> +
> +static const struct spi_nor_fixups evervision_nor_fixups = {
> + .default_init = evervision_nor_default_init,
> +};
> +
> const struct spi_nor_manufacturer spi_nor_everspin = {
> .name = "everspin",
> .parts = everspin_nor_parts,
> .nparts = ARRAY_SIZE(everspin_nor_parts),
> + .fixups = &evervision_nor_fixups,
> };

--
Regards,
Pratyush Yadav