From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F16D3301499 for ; Tue, 18 Nov 2025 12:35:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763469309; cv=none; b=RzG4Z27p3+r9GtCgzqrLAnfV5GQVBZdb9P9t7RNy+RH8NGxZNuOV7Gi9U+OiptpnaBeS8KRntse3AcDuT4WR1aH8AtAnY5GyIHLiBAnb07ZQxTHOfeLoXUYD4M40BUTkputvMOJyr/lZaX8UuUdwKzFUNyPiMmEb32gf+Jr8OiE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763469309; c=relaxed/simple; bh=l8XQvMzxBJv2sM+3H+jof6z7a/FpO+c59Q8kSzXL/Z4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=p81Za4y4H3mmZFoUEkpL217g8VVPp3kHuqHJKMdfnkQJaIwk/zFmCZ2VEr4r48CchD0zHwkKZIkesK5ouxqceLcTfO2YjJddbK8fFm2I56IrCSmDvNYtcrFX/oSmCQHgE7mYWBXdULSc/krGu89+CEVaTIHGyV+NaLo6N3d734U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FGCNMGBh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FGCNMGBh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C4FD0C4CEF5; Tue, 18 Nov 2025 12:35:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763469305; bh=l8XQvMzxBJv2sM+3H+jof6z7a/FpO+c59Q8kSzXL/Z4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=FGCNMGBhg1BBnhQX1+Wp4nJ86KmenvX/thVMsQ0uGa/Y9bZrQBf1iePShDk5E5meV Za7r9npAYq5pA5N115s1sgRpH+B/BRdspykh2cE0rKtRQpAiSe6v0FcpLqc9QkjxqC 2KAy31O59ojoAMZRpzWocCBrH+xMEHxTILtvIxABabE5xQGdDcRe1PQrk9Pu9AlI2Y WsW2Kos+gotzclxFkO0YrLP1nGbKSKQYrBFvMcNeW8Yjb/Rn8o6td+Pdcxzf1e5Azl 7kLMAoWYY53qbY3+rzOlNE4jWWevj3Zq3m7Vpn1Xt5v/T7r9O4NDuQc69mc0eQWl9Z otPn/VE3nkGVg== From: Pratyush Yadav To: Jakub Czapiga Cc: Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Konrad Adamczyk , Adeel Arshad , Mika Westerberg , Kornel Duleba Subject: Re: [PATCH v2] mtd: spi-nor: core: Check read CR support In-Reply-To: <20250919181547.2172319-1-czapiga@google.com> (Jakub Czapiga's message of "Fri, 19 Sep 2025 18:15:47 +0000") References: <20250919181547.2172319-1-czapiga@google.com> Date: Tue, 18 Nov 2025 13:34:59 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Fri, Sep 19 2025, Jakub Czapiga wrote: > Some SPI controllers like Intel's one on the PCI bus do not support > opcode 35h. This opcode is used to read the Configuration Register on > SPI-NOR chips that have 16-bit Status Register configured regardless > of the controller support for it. Adding a check call in the setup step > allows disabling use of the 35h opcode and falling back to the manual > Status Registers management. > > Before: > openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4 > ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = -1 > EOPNOTSUPP > > After: > openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4 > ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = 0 > ioctl(4, MIXER_WRITE(5) or MEMLOCK, {start=0x1800000, length=0x800000}) = 0 > > Suggested-by: Adeel Arshad > Signed-off-by: Jakub Czapiga Reviewed-by: Pratyush Yadav Applied to spi-nor/next. Thanks! BTW, b4 complains that DKIM fails on your email. Please check. [...] -- Regards, Pratyush Yadav