[PATCH v9 0/4] qcom: Add support for IQ-9075-evk board

[PATCH v9 0/4] qcom: Add support for IQ-9075-evk board

[Wasim Nazir]

This series:

Add support for Qualcomm's iq9-evk board using QCS9075 SOC.

QCS9075 is compatible IoT-industrial grade variant of SA8775p SOC.
Unlike QCS9100, it doesn't have safety monitoring feature of
Safety-Island(SAIL) subsystem, which affects thermal management.

In QCS9100 SOC, the safety subsystem monitors all thermal sensors and
does corrective action for each subsystem based on sensor violation
to comply safety standards. But as QCS9075 is non-safe SOC it requires
conventional thermal mitigation for thermal management.
In this series thermal mitigation changes are not included as it needs
more discussion whether to include the change in DT or in drivers.

Below are detailed informations on IQ-9075-evk HW:
------------------------------------------------------
QCS9075 SOM is stacked on top of IQ-9075-evk board.
On top of IQ-9075-evk board additional mezzanine boards can be stacked
in future.
IQ-9075-evk is single board supporting these peripherals:
  - Storage: 2 × 128 GB UFS, micro-SD card, EEPROMs for MACs,
    eMMC on mezzanine card
  - Audio/Video, Camera & Display ports
  - Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD
  - Sensors: IMU
  - PCIe ports
  - USB & UART ports

Currently basic features are enabled to support 'boot to shell'.

---
Changelog:

v9:
  - Retain earlier tags from Rob Herring [1] & Krzysztof Kozlowski [2]
  - v8-link: [3]

v8:
  - Squash UFS support [4] into initial board support patch.
  - Remove uart10 pinctrl settings from board, it is moved to sa8775p.dtsi.
  - Arrange ufs nodes in alphabetical order.
  - v7-link: [5]

[1] https://lore.kernel.org/all/173142574295.951085.7523517676553074543.robh@kernel.org/
[2] https://lore.kernel.org/all/20250430-enlightened-enchanted-jellyfish-7049d0@kuoka/
[3] https://lore.kernel.org/all/20250528122753.3623570-1-quic_wasimn@quicinc.com/
[4] https://lore.kernel.org/all/20250513084309.10275-1-quic_sayalil@quicinc.com/
[5] https://lore.kernel.org/all/20250521140807.3837019-1-quic_wasimn@quicinc.com/


Pratyush Brahma (1):
  arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

Wasim Nazir (3):
  dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board
  arm64: dts: qcom: qcs9075: Introduce QCS9075 SOM
  arm64: dts: qcom: Add support for qcs9075 IQ-9075-EVK

 .../devicetree/bindings/arm/qcom.yaml         |   7 +
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 +++++++
 .../boot/dts/qcom/qcs9075-iq-9075-evk.dts     | 289 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi     |  10 +
 5 files changed, 420 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi


base-commit: 3be1a7a31fbda82f3604b6c31e4f390110de1b46
--
2.49.0

[PATCH v9 1/4] dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board

[Wasim Nazir]

QCS9075 is compatible Industrial-IOT grade variant of SA8775p SOC.
Unlike QCS9100, it doesn't have safety monitoring feature of
Safety-Island(SAIL) subsystem, which affects thermal management.

qcs9075-iq-9075-evk board is based on QCS9075 SOC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 56f78f0f3803..3b2c60af12cd 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -58,6 +58,7 @@ description: |
         qcs8550
         qcm2290
         qcm6490
+        qcs9075
         qcs9100
         qdu1000
         qrb2210
@@ -961,6 +962,12 @@ properties:
               - qcom,sa8775p-ride-r3
           - const: qcom,sa8775p

+      - items:
+          - enum:
+              - qcom,qcs9075-iq-9075-evk
+          - const: qcom,qcs9075
+          - const: qcom,sa8775p
+
       - items:
           - enum:
               - qcom,qcs9100-ride
--
2.49.0

[PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Wasim Nazir]

From: Pratyush Brahma <quic_pbrahma@quicinc.com>

SA8775P has a memory map which caters to the auto specific requirements.
QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
inherit the memory map of SA8775P require a slightly different memory
map as compared to SA8775P auto parts.
This new memory map is applicable for all the IoT boards which inherit
the initial SA8775P memory map. This is not applicable for non-IoT
boards.

Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
introduced as part of firmware updates for IoT. The size and base address
have been updated for video PIL carveout compared to SA8775P since it is
being brought up for the first time on IoT boards. The base addresses
of the rest of the PIL carveouts have been updated to accommodate the
change in size of video since PIL regions are relocatable and their
functionality is not impacted due to this change. The size of camera
pil has also been increased without breaking any feature.

The size of trusted apps carveout has also been reduced since it is
sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
carveout and its corresponding scm reference has been removed as these
are not required for IoT parts.

Incorporate these changes in the updated memory map.

Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
 1 file changed, 113 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi

diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
new file mode 100644
index 000000000000..ff2600eb5e3d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/delete-node/ &pil_camera_mem;
+/delete-node/ &pil_adsp_mem;
+/delete-node/ &pil_gdsp0_mem;
+/delete-node/ &pil_gdsp1_mem;
+/delete-node/ &pil_cdsp0_mem;
+/delete-node/ &pil_gpu_mem;
+/delete-node/ &pil_cdsp1_mem;
+/delete-node/ &pil_cvp_mem;
+/delete-node/ &pil_video_mem;
+/delete-node/ &audio_mdf_mem;
+/delete-node/ &trusted_apps_mem;
+/delete-node/ &hyptz_reserved_mem;
+/delete-node/ &tz_ffi_mem;
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gunyah_md_mem: gunyah-md@91a80000 {
+			reg = <0x0 0x91a80000 0x0 0x80000>;
+			no-map;
+		};
+
+		pil_camera_mem: pil-camera@95200000 {
+			reg = <0x0 0x95200000 0x0 0x700000>;
+			no-map;
+		};
+
+		pil_adsp_mem: pil-adsp@95900000 {
+			reg = <0x0 0x95900000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		q6_adsp_dtb_mem: q6-adsp-dtb@97700000 {
+			reg = <0x0 0x97700000 0x0 0x80000>;
+			no-map;
+		};
+
+		q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 {
+			reg = <0x0 0x97780000 0x0 0x80000>;
+			no-map;
+		};
+
+		pil_gdsp0_mem: pil-gdsp0@97800000 {
+			reg = <0x0 0x97800000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gdsp1_mem: pil-gdsp1@99600000 {
+			reg = <0x0 0x99600000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 {
+			reg = <0x0 0x9b400000 0x0 0x80000>;
+			no-map;
+		};
+
+		q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 {
+			reg = <0x0 0x9b480000 0x0 0x80000>;
+			no-map;
+		};
+
+		pil_cdsp0_mem: pil-cdsp0@9b500000 {
+			reg = <0x0 0x9b500000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gpu_mem: pil-gpu@9d300000 {
+			reg = <0x0 0x9d300000 0x0 0x2000>;
+			no-map;
+		};
+
+		q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 {
+			reg = <0x0 0x9d380000 0x0 0x80000>;
+			no-map;
+		};
+
+		pil_cdsp1_mem: pil-cdsp1@9d400000 {
+			reg = <0x0 0x9d400000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_cvp_mem: pil-cvp@9f200000 {
+			reg = <0x0 0x9f200000 0x0 0x700000>;
+			no-map;
+		};
+
+		pil_video_mem: pil-video@9f900000 {
+			reg = <0x0 0x9f900000 0x0 0x1000000>;
+			no-map;
+		};
+
+		trusted_apps_mem: trusted-apps@d1900000 {
+			reg = <0x0 0xd1900000 0x0 0x1c00000>;
+			no-map;
+		};
+	};
+
+	firmware {
+		scm {
+			/delete-property/ memory-region;
+		};
+	};
+};
--
2.49.0

[PATCH v9 3/4] arm64: dts: qcom: qcs9075: Introduce QCS9075 SOM

[Wasim Nazir]

QCS9075 is an IoT variant of SA8775P SOC, most notably without
safety monitoring feature of Safety Island(SAIL) subsystem.
Add qcs9075-som.dtsi to specifies QCS9075 based SOM having SOC,
PMICs, Memory-map updates.
Use this SOM for qcs9075-iq-9075-evk board.

Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi

diff --git a/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi b/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
new file mode 100644
index 000000000000..552e40c95e06
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sa8775p.dtsi"
+#include "iq9-reserved-memory.dtsi"
+#include "sa8775p-pmics.dtsi"
--
2.49.0

[PATCH v9 4/4] arm64: dts: qcom: Add support for qcs9075 IQ-9075-EVK

[Wasim Nazir]

Add initial device tree support for IQ-9075-EVK board,
based on Qualcomm's QCS9075 SOC.

Implement basic features like uart/ufs to enable boot to shell.

Co-developed-by: Rakesh Kota <quic_kotarake@quicinc.com>
Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com>
Co-developed-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/qcs9075-iq-9075-evk.dts     | 289 ++++++++++++++++++
 2 files changed, 290 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 669b888b27a1..77501a13d91e 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-industrial-mezzanine.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-vision-mezzanine.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8300-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs9075-iq-9075-evk.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride-r3.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qdu1000-idp.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
new file mode 100644
index 000000000000..f1f725691ba2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "qcs9075-som.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IQ 9075 EVK";
+	compatible = "qcom,qcs9075-iq-9075-evk", "qcom,qcs9075", "qcom,sa8775p";
+
+	aliases {
+		serial0 = &uart10;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vreg_s4a: smps4 {
+			regulator-name = "vreg_s4a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1816000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5a: smps5 {
+			regulator-name = "vreg_s5a";
+			regulator-min-microvolt = <1850000>;
+			regulator-max-microvolt = <1996000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s9a: smps9 {
+			regulator-name = "vreg_s9a";
+			regulator-min-microvolt = <535000>;
+			regulator-max-microvolt = <1120000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4a: ldo4 {
+			regulator-name = "vreg_l4a";
+			regulator-min-microvolt = <788000>;
+			regulator-max-microvolt = <1050000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5a: ldo5 {
+			regulator-name = "vreg_l5a";
+			regulator-min-microvolt = <870000>;
+			regulator-max-microvolt = <950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6a: ldo6 {
+			regulator-name = "vreg_l6a";
+			regulator-min-microvolt = <870000>;
+			regulator-max-microvolt = <970000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a: ldo7 {
+			regulator-name = "vreg_l7a";
+			regulator-min-microvolt = <720000>;
+			regulator-max-microvolt = <950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a: ldo8 {
+			regulator-name = "vreg_l8a";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9a: ldo9 {
+			regulator-name = "vreg_l9a";
+			regulator-min-microvolt = <2970000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vreg_l1c: ldo1 {
+			regulator-name = "vreg_l1c";
+			regulator-min-microvolt = <1140000>;
+			regulator-max-microvolt = <1260000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c: ldo2 {
+			regulator-name = "vreg_l2c";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c: ldo3 {
+			regulator-name = "vreg_l3c";
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4c: ldo4 {
+			regulator-name = "vreg_l4c";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5c: ldo5 {
+			regulator-name = "vreg_l5c";
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6c: ldo6 {
+			regulator-name = "vreg_l6c";
+			regulator-min-microvolt = <1620000>;
+			regulator-max-microvolt = <1980000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7c: ldo7 {
+			regulator-name = "vreg_l7c";
+			regulator-min-microvolt = <1620000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8c: ldo8 {
+			regulator-name = "vreg_l8c";
+			regulator-min-microvolt = <2400000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9c: ldo9 {
+			regulator-name = "vreg_l9c";
+			regulator-min-microvolt = <1650000>;
+			regulator-max-microvolt = <2700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vreg_s4e: smps4 {
+			regulator-name = "vreg_s4e";
+			regulator-min-microvolt = <970000>;
+			regulator-max-microvolt = <1520000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s7e: smps7 {
+			regulator-name = "vreg_s7e";
+			regulator-min-microvolt = <1010000>;
+			regulator-max-microvolt = <1170000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s9e: smps9 {
+			regulator-name = "vreg_s9e";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <570000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6e: ldo6 {
+			regulator-name = "vreg_l6e";
+			regulator-min-microvolt = <1280000>;
+			regulator-max-microvolt = <1450000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8e: ldo8 {
+			regulator-name = "vreg_l8e";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32768>;
+};
+
+&uart10 {
+	compatible = "qcom,geni-debug-uart";
+	pinctrl-0 = <&qup_uart10_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l8a>;
+	vcc-max-microamp = <1100000>;
+	vccq-supply = <&vreg_l4c>;
+	vccq-max-microamp = <1200000>;
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l4a>;
+	vdda-pll-supply = <&vreg_l1c>;
+
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <38400000>;
+};
--
2.49.0

Re: [PATCH v9 4/4] arm64: dts: qcom: Add support for qcs9075 IQ-9075-EVK

[Konrad Dybcio]

On 5/30/25 11:28 AM, Wasim Nazir wrote:
> Add initial device tree support for IQ-9075-EVK board,
> based on Qualcomm's QCS9075 SOC.
> 
> Implement basic features like uart/ufs to enable boot to shell.
> 
> Co-developed-by: Rakesh Kota <quic_kotarake@quicinc.com>
> Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com>
> Co-developed-by: Sayali Lokhande <quic_sayalil@quicinc.com>
> Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v9 0/4] qcom: Add support for IQ-9075-evk board

[Rob Herring (Arm)]

On Fri, 30 May 2025 14:58:43 +0530, Wasim Nazir wrote:
> This series:
> 
> Add support for Qualcomm's iq9-evk board using QCS9075 SOC.
> 
> QCS9075 is compatible IoT-industrial grade variant of SA8775p SOC.
> Unlike QCS9100, it doesn't have safety monitoring feature of
> Safety-Island(SAIL) subsystem, which affects thermal management.
> 
> In QCS9100 SOC, the safety subsystem monitors all thermal sensors and
> does corrective action for each subsystem based on sensor violation
> to comply safety standards. But as QCS9075 is non-safe SOC it requires
> conventional thermal mitigation for thermal management.
> In this series thermal mitigation changes are not included as it needs
> more discussion whether to include the change in DT or in drivers.
> 
> Below are detailed informations on IQ-9075-evk HW:
> ------------------------------------------------------
> QCS9075 SOM is stacked on top of IQ-9075-evk board.
> On top of IQ-9075-evk board additional mezzanine boards can be stacked
> in future.
> IQ-9075-evk is single board supporting these peripherals:
>   - Storage: 2 × 128 GB UFS, micro-SD card, EEPROMs for MACs,
>     eMMC on mezzanine card
>   - Audio/Video, Camera & Display ports
>   - Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD
>   - Sensors: IMU
>   - PCIe ports
>   - USB & UART ports
> 
> Currently basic features are enabled to support 'boot to shell'.
> 
> ---
> Changelog:
> 
> v9:
>   - Retain earlier tags from Rob Herring [1] & Krzysztof Kozlowski [2]
>   - v8-link: [3]
> 
> v8:
>   - Squash UFS support [4] into initial board support patch.
>   - Remove uart10 pinctrl settings from board, it is moved to sa8775p.dtsi.
>   - Arrange ufs nodes in alphabetical order.
>   - v7-link: [5]
> 
> [1] https://lore.kernel.org/all/173142574295.951085.7523517676553074543.robh@kernel.org/
> [2] https://lore.kernel.org/all/20250430-enlightened-enchanted-jellyfish-7049d0@kuoka/
> [3] https://lore.kernel.org/all/20250528122753.3623570-1-quic_wasimn@quicinc.com/
> [4] https://lore.kernel.org/all/20250513084309.10275-1-quic_sayalil@quicinc.com/
> [5] https://lore.kernel.org/all/20250521140807.3837019-1-quic_wasimn@quicinc.com/
> 
> 
> Pratyush Brahma (1):
>   arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075
> 
> Wasim Nazir (3):
>   dt-bindings: arm: qcom: Add bindings for QCS9075 SOC based board
>   arm64: dts: qcom: qcs9075: Introduce QCS9075 SOM
>   arm64: dts: qcom: Add support for qcs9075 IQ-9075-EVK
> 
>  .../devicetree/bindings/arm/qcom.yaml         |   7 +
>  arch/arm64/boot/dts/qcom/Makefile             |   1 +
>  .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 +++++++
>  .../boot/dts/qcom/qcs9075-iq-9075-evk.dts     | 289 ++++++++++++++++++
>  arch/arm64/boot/dts/qcom/qcs9075-som.dtsi     |  10 +
>  5 files changed, 420 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
>  create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
> 
> 
> base-commit: 3be1a7a31fbda82f3604b6c31e4f390110de1b46
> --
> 2.49.0
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: using specified base-commit 3be1a7a31fbda82f3604b6c31e4f390110de1b46

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250530092850.631831-1-quic_wasimn@quicinc.com:

arch/arm64/boot/dts/qcom/qcs9075-iq-9075-evk.dtb: display-controller@ae01000 (qcom,sa8775p-dpu): clock-names:0: 'nrt_bus' was expected
	from schema $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#

Re: [PATCH v9 3/4] arm64: dts: qcom: qcs9075: Introduce QCS9075 SOM

[Dmitry Baryshkov]

On Fri, May 30, 2025 at 02:58:46PM +0530, Wasim Nazir wrote:
> QCS9075 is an IoT variant of SA8775P SOC, most notably without
> safety monitoring feature of Safety Island(SAIL) subsystem.
> Add qcs9075-som.dtsi to specifies QCS9075 based SOM having SOC,
> PMICs, Memory-map updates.
> Use this SOM for qcs9075-iq-9075-evk board.

No, you are not using the newly added SoM, you are just adding it. If
you really want to use it for the EVK board, squash this commit into the
next one.

> 
> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs9075-som.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi b/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
> new file mode 100644
> index 000000000000..552e40c95e06
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "sa8775p.dtsi"
> +#include "iq9-reserved-memory.dtsi"
> +#include "sa8775p-pmics.dtsi"
> --
> 2.49.0
> 

-- 
With best wishes
Dmitry

Re: [PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Bjorn Andersson]

On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote:
> From: Pratyush Brahma <quic_pbrahma@quicinc.com>
> 
> SA8775P has a memory map which caters to the auto specific requirements.

I thought SA8775P was the IoT platform and SA8255P was the automotive
one. Has this changed?

> QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
> inherit the memory map of SA8775P require a slightly different memory
> map as compared to SA8775P auto parts.
> This new memory map is applicable for all the IoT boards which inherit
> the initial SA8775P memory map. This is not applicable for non-IoT

Is there are platform out there that actually uses the "initial SA8775P
memory map"?

> boards.
> 
> Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
> introduced as part of firmware updates for IoT. The size and base address
> have been updated for video PIL carveout compared to SA8775P since it is
> being brought up for the first time on IoT boards. The base addresses
> of the rest of the PIL carveouts have been updated to accommodate the
> change in size of video since PIL regions are relocatable and their
> functionality is not impacted due to this change. The size of camera
> pil has also been increased without breaking any feature.
> 
> The size of trusted apps carveout has also been reduced since it is
> sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
> carveout and its corresponding scm reference has been removed as these
> are not required for IoT parts.
> 
> Incorporate these changes in the updated memory map.
> 
> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> ---
>  .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
>  1 file changed, 113 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> new file mode 100644
> index 000000000000..ff2600eb5e3d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi

The naming convention is <soc>-<something>.dtsi and I don't see any
other uses of the "iq9" naming.

> @@ -0,0 +1,113 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +

Why is there a blank space here?

Regards,
Bjorn

> +/*
> + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/delete-node/ &pil_camera_mem;
> +/delete-node/ &pil_adsp_mem;
> +/delete-node/ &pil_gdsp0_mem;
> +/delete-node/ &pil_gdsp1_mem;
> +/delete-node/ &pil_cdsp0_mem;
> +/delete-node/ &pil_gpu_mem;
> +/delete-node/ &pil_cdsp1_mem;
> +/delete-node/ &pil_cvp_mem;
> +/delete-node/ &pil_video_mem;
> +/delete-node/ &audio_mdf_mem;
> +/delete-node/ &trusted_apps_mem;
> +/delete-node/ &hyptz_reserved_mem;
> +/delete-node/ &tz_ffi_mem;
> +
> +/ {
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		gunyah_md_mem: gunyah-md@91a80000 {
> +			reg = <0x0 0x91a80000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		pil_camera_mem: pil-camera@95200000 {
> +			reg = <0x0 0x95200000 0x0 0x700000>;
> +			no-map;
> +		};
> +
> +		pil_adsp_mem: pil-adsp@95900000 {
> +			reg = <0x0 0x95900000 0x0 0x1e00000>;
> +			no-map;
> +		};
> +
> +		q6_adsp_dtb_mem: q6-adsp-dtb@97700000 {
> +			reg = <0x0 0x97700000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 {
> +			reg = <0x0 0x97780000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		pil_gdsp0_mem: pil-gdsp0@97800000 {
> +			reg = <0x0 0x97800000 0x0 0x1e00000>;
> +			no-map;
> +		};
> +
> +		pil_gdsp1_mem: pil-gdsp1@99600000 {
> +			reg = <0x0 0x99600000 0x0 0x1e00000>;
> +			no-map;
> +		};
> +
> +		q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 {
> +			reg = <0x0 0x9b400000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 {
> +			reg = <0x0 0x9b480000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		pil_cdsp0_mem: pil-cdsp0@9b500000 {
> +			reg = <0x0 0x9b500000 0x0 0x1e00000>;
> +			no-map;
> +		};
> +
> +		pil_gpu_mem: pil-gpu@9d300000 {
> +			reg = <0x0 0x9d300000 0x0 0x2000>;
> +			no-map;
> +		};
> +
> +		q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 {
> +			reg = <0x0 0x9d380000 0x0 0x80000>;
> +			no-map;
> +		};
> +
> +		pil_cdsp1_mem: pil-cdsp1@9d400000 {
> +			reg = <0x0 0x9d400000 0x0 0x1e00000>;
> +			no-map;
> +		};
> +
> +		pil_cvp_mem: pil-cvp@9f200000 {
> +			reg = <0x0 0x9f200000 0x0 0x700000>;
> +			no-map;
> +		};
> +
> +		pil_video_mem: pil-video@9f900000 {
> +			reg = <0x0 0x9f900000 0x0 0x1000000>;
> +			no-map;
> +		};
> +
> +		trusted_apps_mem: trusted-apps@d1900000 {
> +			reg = <0x0 0xd1900000 0x0 0x1c00000>;
> +			no-map;
> +		};
> +	};
> +
> +	firmware {
> +		scm {
> +			/delete-property/ memory-region;
> +		};
> +	};
> +};
> --
> 2.49.0
> 

Re: [PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Wasim Nazir]

On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote:
> On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote:
> > From: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > 
> > SA8775P has a memory map which caters to the auto specific requirements.
> 
> I thought SA8775P was the IoT platform and SA8255P was the automotive
> one. Has this changed?

Both SA8775P & SA8255P is for auto but former one is non-SCMI based while
the later one is SCMI based chip.

Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT.

> 
> > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
> > inherit the memory map of SA8775P require a slightly different memory
> > map as compared to SA8775P auto parts.
> > This new memory map is applicable for all the IoT boards which inherit
> > the initial SA8775P memory map. This is not applicable for non-IoT
> 
> Is there are platform out there that actually uses the "initial SA8775P
> memory map"?

Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory
map.

> 
> > boards.
> > 
> > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
> > introduced as part of firmware updates for IoT. The size and base address
> > have been updated for video PIL carveout compared to SA8775P since it is
> > being brought up for the first time on IoT boards. The base addresses
> > of the rest of the PIL carveouts have been updated to accommodate the
> > change in size of video since PIL regions are relocatable and their
> > functionality is not impacted due to this change. The size of camera
> > pil has also been increased without breaking any feature.
> > 
> > The size of trusted apps carveout has also been reduced since it is
> > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
> > carveout and its corresponding scm reference has been removed as these
> > are not required for IoT parts.
> > 
> > Incorporate these changes in the updated memory map.
> > 
> > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
> > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > ---
> >  .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
> >  1 file changed, 113 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > new file mode 100644
> > index 000000000000..ff2600eb5e3d
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> 
> The naming convention is <soc>-<something>.dtsi and I don't see any
> other uses of the "iq9" naming.

As this new memory map is common for IQ9 series of SoC (QCS9100 &
QCS9075), so we have used its common name.
Once the DT structure for QCS9100 is refactored, we would update this
common file there.

> 
> > @@ -0,0 +1,113 @@
> > +// SPDX-License-Identifier: BSD-3-Clause
> > +
> 
> Why is there a blank space here?

Will remove this in next patch.

> 
> Regards,
> Bjorn

Regards,
Wasim
> 
> > +/*
> > + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
> > + */
> > +
> > +/delete-node/ &pil_camera_mem;
> > +/delete-node/ &pil_adsp_mem;
> > +/delete-node/ &pil_gdsp0_mem;
> > +/delete-node/ &pil_gdsp1_mem;
> > +/delete-node/ &pil_cdsp0_mem;
> > +/delete-node/ &pil_gpu_mem;
> > +/delete-node/ &pil_cdsp1_mem;
> > +/delete-node/ &pil_cvp_mem;
> > +/delete-node/ &pil_video_mem;
> > +/delete-node/ &audio_mdf_mem;
> > +/delete-node/ &trusted_apps_mem;
> > +/delete-node/ &hyptz_reserved_mem;
> > +/delete-node/ &tz_ffi_mem;
> > +
> > +/ {
> > +	reserved-memory {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		gunyah_md_mem: gunyah-md@91a80000 {
> > +			reg = <0x0 0x91a80000 0x0 0x80000>;
> > +			no-map;
> > +		};
> > +
> > +		pil_camera_mem: pil-camera@95200000 {
> > +			reg = <0x0 0x95200000 0x0 0x700000>;
> > +			no-map;
> > +		};
> > +
> > +		pil_adsp_mem: pil-adsp@95900000 {
> > +			reg = <0x0 0x95900000 0x0 0x1e00000>;
> > +			no-map;
> > +		};
> > +
> > +		q6_adsp_dtb_mem: q6-adsp-dtb@97700000 {
> > +			reg = <0x0 0x97700000 0x0 0x80000>;
> > +			no-map;
> > +		};
> > +
> > +		q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 {
> > +			reg = <0x0 0x97780000 0x0 0x80000>;
> > +			no-map;
> > +		};
> > +
> > +		pil_gdsp0_mem: pil-gdsp0@97800000 {
> > +			reg = <0x0 0x97800000 0x0 0x1e00000>;
> > +			no-map;
> > +		};
> > +
> > +		pil_gdsp1_mem: pil-gdsp1@99600000 {
> > +			reg = <0x0 0x99600000 0x0 0x1e00000>;
> > +			no-map;
> > +		};
> > +
> > +		q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 {
> > +			reg = <0x0 0x9b400000 0x0 0x80000>;
> > +			no-map;
> > +		};
> > +
> > +		q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 {
> > +			reg = <0x0 0x9b480000 0x0 0x80000>;
> > +			no-map;
> > +		};
> > +
> > +		pil_cdsp0_mem: pil-cdsp0@9b500000 {
> > +			reg = <0x0 0x9b500000 0x0 0x1e00000>;
> > +			no-map;
> > +		};
> > +
> > +		pil_gpu_mem: pil-gpu@9d300000 {
> > +			reg = <0x0 0x9d300000 0x0 0x2000>;
> > +			no-map;
> > +		};
> > +
> > +		q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 {
> > +			reg = <0x0 0x9d380000 0x0 0x80000>;
> > +			no-map;
> > +		};
> > +
> > +		pil_cdsp1_mem: pil-cdsp1@9d400000 {
> > +			reg = <0x0 0x9d400000 0x0 0x1e00000>;
> > +			no-map;
> > +		};
> > +
> > +		pil_cvp_mem: pil-cvp@9f200000 {
> > +			reg = <0x0 0x9f200000 0x0 0x700000>;
> > +			no-map;
> > +		};
> > +
> > +		pil_video_mem: pil-video@9f900000 {
> > +			reg = <0x0 0x9f900000 0x0 0x1000000>;
> > +			no-map;
> > +		};
> > +
> > +		trusted_apps_mem: trusted-apps@d1900000 {
> > +			reg = <0x0 0xd1900000 0x0 0x1c00000>;
> > +			no-map;
> > +		};
> > +	};
> > +
> > +	firmware {
> > +		scm {
> > +			/delete-property/ memory-region;
> > +		};
> > +	};
> > +};
> > --
> > 2.49.0
> > 

Re: [PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Dmitry Baryshkov]

On Wed, Jun 04, 2025 at 03:05:55PM +0530, Wasim Nazir wrote:
> On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote:
> > On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote:
> > > From: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > 
> > > SA8775P has a memory map which caters to the auto specific requirements.
> > 
> > I thought SA8775P was the IoT platform and SA8255P was the automotive
> > one. Has this changed?
> 
> Both SA8775P & SA8255P is for auto but former one is non-SCMI based while
> the later one is SCMI based chip.
> 
> Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT.
> 
> > 
> > > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
> > > inherit the memory map of SA8775P require a slightly different memory
> > > map as compared to SA8775P auto parts.
> > > This new memory map is applicable for all the IoT boards which inherit
> > > the initial SA8775P memory map. This is not applicable for non-IoT
> > 
> > Is there are platform out there that actually uses the "initial SA8775P
> > memory map"?
> 
> Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory
> map.
> 
> > 
> > > boards.
> > > 
> > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
> > > introduced as part of firmware updates for IoT. The size and base address
> > > have been updated for video PIL carveout compared to SA8775P since it is
> > > being brought up for the first time on IoT boards. The base addresses
> > > of the rest of the PIL carveouts have been updated to accommodate the
> > > change in size of video since PIL regions are relocatable and their
> > > functionality is not impacted due to this change. The size of camera
> > > pil has also been increased without breaking any feature.
> > > 
> > > The size of trusted apps carveout has also been reduced since it is
> > > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
> > > carveout and its corresponding scm reference has been removed as these
> > > are not required for IoT parts.
> > > 
> > > Incorporate these changes in the updated memory map.
> > > 
> > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
> > > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > > ---
> > >  .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
> > >  1 file changed, 113 insertions(+)
> > >  create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > new file mode 100644
> > > index 000000000000..ff2600eb5e3d
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > 
> > The naming convention is <soc>-<something>.dtsi and I don't see any
> > other uses of the "iq9" naming.
> 
> As this new memory map is common for IQ9 series of SoC (QCS9100 &
> QCS9075), so we have used its common name.

IQ9 name is not known or visible outside of this commit.

> Once the DT structure for QCS9100 is refactored, we would update this
> common file there.

Can you refactor it first?

> 
> > 

-- 
With best wishes
Dmitry

Re: [PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Wasim Nazir]

On Wed, Jun 04, 2025 at 04:21:46PM +0300, Dmitry Baryshkov wrote:
> On Wed, Jun 04, 2025 at 03:05:55PM +0530, Wasim Nazir wrote:
> > On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote:
> > > On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote:
> > > > From: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > 
> > > > SA8775P has a memory map which caters to the auto specific requirements.
> > > 
> > > I thought SA8775P was the IoT platform and SA8255P was the automotive
> > > one. Has this changed?
> > 
> > Both SA8775P & SA8255P is for auto but former one is non-SCMI based while
> > the later one is SCMI based chip.
> > 
> > Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT.
> > 
> > > 
> > > > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
> > > > inherit the memory map of SA8775P require a slightly different memory
> > > > map as compared to SA8775P auto parts.
> > > > This new memory map is applicable for all the IoT boards which inherit
> > > > the initial SA8775P memory map. This is not applicable for non-IoT
> > > 
> > > Is there are platform out there that actually uses the "initial SA8775P
> > > memory map"?
> > 
> > Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory
> > map.
> > 
> > > 
> > > > boards.
> > > > 
> > > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
> > > > introduced as part of firmware updates for IoT. The size and base address
> > > > have been updated for video PIL carveout compared to SA8775P since it is
> > > > being brought up for the first time on IoT boards. The base addresses
> > > > of the rest of the PIL carveouts have been updated to accommodate the
> > > > change in size of video since PIL regions are relocatable and their
> > > > functionality is not impacted due to this change. The size of camera
> > > > pil has also been increased without breaking any feature.
> > > > 
> > > > The size of trusted apps carveout has also been reduced since it is
> > > > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
> > > > carveout and its corresponding scm reference has been removed as these
> > > > are not required for IoT parts.
> > > > 
> > > > Incorporate these changes in the updated memory map.
> > > > 
> > > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
> > > > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > > > ---
> > > >  .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
> > > >  1 file changed, 113 insertions(+)
> > > >  create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > new file mode 100644
> > > > index 000000000000..ff2600eb5e3d
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > 
> > > The naming convention is <soc>-<something>.dtsi and I don't see any
> > > other uses of the "iq9" naming.
> > 
> > As this new memory map is common for IQ9 series of SoC (QCS9100 &
> > QCS9075), so we have used its common name.
> 
> IQ9 name is not known or visible outside of this commit.

Are you referring to add the same in cover-letter?

> 
> > Once the DT structure for QCS9100 is refactored, we would update this
> > common file there.
> 
> Can you refactor it first?

This refactoring involves changes in all the ride/ride-r3 boards which
are based on sa8775p & qcs9100. Even though we had sent v0[1] but we still
need to conclude on the final structure. Since, ethernet is broken in upstream,
we are working on its fix before sending another series.

Hence, we want to proceed for iq9075-evk for now and once qcs9100 is
finalized, we can use the memory-map there.

But to avoid this dependency and to proceed with iq9075-evk alone,
I can rename it to qcs9075-reserved-memory.dtsi.

Let me know if that works here.

[1] https://lore.kernel.org/all/20250507065116.353114-1-quic_wasimn@quicinc.com/

> 
> > 
> > > 
> 
> -- 
> With best wishes
> Dmitry

Regards,
Wasim

Re: [PATCH v9 3/4] arm64: dts: qcom: qcs9075: Introduce QCS9075 SOM

[Wasim Nazir]

On Mon, Jun 02, 2025 at 10:03:19AM +0300, Dmitry Baryshkov wrote:
> On Fri, May 30, 2025 at 02:58:46PM +0530, Wasim Nazir wrote:
> > QCS9075 is an IoT variant of SA8775P SOC, most notably without
> > safety monitoring feature of Safety Island(SAIL) subsystem.
> > Add qcs9075-som.dtsi to specifies QCS9075 based SOM having SOC,
> > PMICs, Memory-map updates.
> > Use this SOM for qcs9075-iq-9075-evk board.
> 
> No, you are not using the newly added SoM, you are just adding it. If
> you really want to use it for the EVK board, squash this commit into the
> next one.

Sure, will squash it.

> 
> > 
> > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > ---
> >  arch/arm64/boot/dts/qcom/qcs9075-som.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi b/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
> > new file mode 100644
> > index 000000000000..552e40c95e06
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/qcs9075-som.dtsi
> > @@ -0,0 +1,10 @@
> > +// SPDX-License-Identifier: BSD-3-Clause
> > +/*
> > + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "sa8775p.dtsi"
> > +#include "iq9-reserved-memory.dtsi"
> > +#include "sa8775p-pmics.dtsi"
> > --
> > 2.49.0
> > 
> 
> -- 
> With best wishes
> Dmitry

-- 
Regards,
Wasim

Re: [PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Wasim Nazir]

On Wed, Jun 04, 2025 at 09:54:38PM +0530, Wasim Nazir wrote:
> On Wed, Jun 04, 2025 at 04:21:46PM +0300, Dmitry Baryshkov wrote:
> > On Wed, Jun 04, 2025 at 03:05:55PM +0530, Wasim Nazir wrote:
> > > On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote:
> > > > On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote:
> > > > > From: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > > 
> > > > > SA8775P has a memory map which caters to the auto specific requirements.
> > > > 
> > > > I thought SA8775P was the IoT platform and SA8255P was the automotive
> > > > one. Has this changed?
> > > 
> > > Both SA8775P & SA8255P is for auto but former one is non-SCMI based while
> > > the later one is SCMI based chip.
> > > 
> > > Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT.
> > > 
> > > > 
> > > > > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
> > > > > inherit the memory map of SA8775P require a slightly different memory
> > > > > map as compared to SA8775P auto parts.
> > > > > This new memory map is applicable for all the IoT boards which inherit
> > > > > the initial SA8775P memory map. This is not applicable for non-IoT
> > > > 
> > > > Is there are platform out there that actually uses the "initial SA8775P
> > > > memory map"?
> > > 
> > > Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory
> > > map.
> > > 
> > > > 
> > > > > boards.
> > > > > 
> > > > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
> > > > > introduced as part of firmware updates for IoT. The size and base address
> > > > > have been updated for video PIL carveout compared to SA8775P since it is
> > > > > being brought up for the first time on IoT boards. The base addresses
> > > > > of the rest of the PIL carveouts have been updated to accommodate the
> > > > > change in size of video since PIL regions are relocatable and their
> > > > > functionality is not impacted due to this change. The size of camera
> > > > > pil has also been increased without breaking any feature.
> > > > > 
> > > > > The size of trusted apps carveout has also been reduced since it is
> > > > > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
> > > > > carveout and its corresponding scm reference has been removed as these
> > > > > are not required for IoT parts.
> > > > > 
> > > > > Incorporate these changes in the updated memory map.
> > > > > 
> > > > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
> > > > > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > > > > ---
> > > > >  .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
> > > > >  1 file changed, 113 insertions(+)
> > > > >  create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > new file mode 100644
> > > > > index 000000000000..ff2600eb5e3d
> > > > > --- /dev/null
> > > > > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > 
> > > > The naming convention is <soc>-<something>.dtsi and I don't see any
> > > > other uses of the "iq9" naming.
> > > 
> > > As this new memory map is common for IQ9 series of SoC (QCS9100 &
> > > QCS9075), so we have used its common name.
> > 
> > IQ9 name is not known or visible outside of this commit.
> 
> Are you referring to add the same in cover-letter?
> 
> > 
> > > Once the DT structure for QCS9100 is refactored, we would update this
> > > common file there.
> > 
> > Can you refactor it first?
> 
> This refactoring involves changes in all the ride/ride-r3 boards which
> are based on sa8775p & qcs9100. Even though we had sent v0[1] but we still
> need to conclude on the final structure. Since, ethernet is broken in upstream,
> we are working on its fix before sending another series.
> 
> Hence, we want to proceed for iq9075-evk for now and once qcs9100 is
> finalized, we can use the memory-map there.
> 
> But to avoid this dependency and to proceed with iq9075-evk alone,
> I can rename it to qcs9075-reserved-memory.dtsi.
> 
> Let me know if that works here.
> 
> [1] https://lore.kernel.org/all/20250507065116.353114-1-quic_wasimn@quicinc.com/

Hi Dmitry,

Shall I proceed with qcs9075-reserved-memory.dtsi or do you have any
other suggestion that we should discuss?

Aparently, this series is for qcs9075 only so using exact (not common)
name also aligns the naming format.

> 
> > 
> > > 
> > > > 
> > 
> > -- 
> > With best wishes
> > Dmitry
> 
> Regards,
> Wasim

-- 
Regards,
Wasim

Re: [PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Dmitry Baryshkov]

On Fri, Jun 06, 2025 at 02:02:50PM +0530, Wasim Nazir wrote:
> On Wed, Jun 04, 2025 at 09:54:38PM +0530, Wasim Nazir wrote:
> > On Wed, Jun 04, 2025 at 04:21:46PM +0300, Dmitry Baryshkov wrote:
> > > On Wed, Jun 04, 2025 at 03:05:55PM +0530, Wasim Nazir wrote:
> > > > On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote:
> > > > > On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote:
> > > > > > From: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > > > 
> > > > > > SA8775P has a memory map which caters to the auto specific requirements.
> > > > > 
> > > > > I thought SA8775P was the IoT platform and SA8255P was the automotive
> > > > > one. Has this changed?
> > > > 
> > > > Both SA8775P & SA8255P is for auto but former one is non-SCMI based while
> > > > the later one is SCMI based chip.
> > > > 
> > > > Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT.
> > > > 
> > > > > 
> > > > > > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
> > > > > > inherit the memory map of SA8775P require a slightly different memory
> > > > > > map as compared to SA8775P auto parts.
> > > > > > This new memory map is applicable for all the IoT boards which inherit
> > > > > > the initial SA8775P memory map. This is not applicable for non-IoT
> > > > > 
> > > > > Is there are platform out there that actually uses the "initial SA8775P
> > > > > memory map"?
> > > > 
> > > > Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory
> > > > map.
> > > > 
> > > > > 
> > > > > > boards.
> > > > > > 
> > > > > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
> > > > > > introduced as part of firmware updates for IoT. The size and base address
> > > > > > have been updated for video PIL carveout compared to SA8775P since it is
> > > > > > being brought up for the first time on IoT boards. The base addresses
> > > > > > of the rest of the PIL carveouts have been updated to accommodate the
> > > > > > change in size of video since PIL regions are relocatable and their
> > > > > > functionality is not impacted due to this change. The size of camera
> > > > > > pil has also been increased without breaking any feature.
> > > > > > 
> > > > > > The size of trusted apps carveout has also been reduced since it is
> > > > > > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
> > > > > > carveout and its corresponding scm reference has been removed as these
> > > > > > are not required for IoT parts.
> > > > > > 
> > > > > > Incorporate these changes in the updated memory map.
> > > > > > 
> > > > > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > > > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
> > > > > > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > > > > > ---
> > > > > >  .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
> > > > > >  1 file changed, 113 insertions(+)
> > > > > >  create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > > 
> > > > > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > > new file mode 100644
> > > > > > index 000000000000..ff2600eb5e3d
> > > > > > --- /dev/null
> > > > > > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > 
> > > > > The naming convention is <soc>-<something>.dtsi and I don't see any
> > > > > other uses of the "iq9" naming.
> > > > 
> > > > As this new memory map is common for IQ9 series of SoC (QCS9100 &
> > > > QCS9075), so we have used its common name.
> > > 
> > > IQ9 name is not known or visible outside of this commit.
> > 
> > Are you referring to add the same in cover-letter?
> > 
> > > 
> > > > Once the DT structure for QCS9100 is refactored, we would update this
> > > > common file there.
> > > 
> > > Can you refactor it first?
> > 
> > This refactoring involves changes in all the ride/ride-r3 boards which
> > are based on sa8775p & qcs9100. Even though we had sent v0[1] but we still
> > need to conclude on the final structure. Since, ethernet is broken in upstream,
> > we are working on its fix before sending another series.
> > 
> > Hence, we want to proceed for iq9075-evk for now and once qcs9100 is
> > finalized, we can use the memory-map there.
> > 
> > But to avoid this dependency and to proceed with iq9075-evk alone,
> > I can rename it to qcs9075-reserved-memory.dtsi.
> > 
> > Let me know if that works here.
> > 
> > [1] https://lore.kernel.org/all/20250507065116.353114-1-quic_wasimn@quicinc.com/
> 
> Hi Dmitry,
> 
> Shall I proceed with qcs9075-reserved-memory.dtsi or do you have any
> other suggestion that we should discuss?
> 
> Aparently, this series is for qcs9075 only so using exact (not common)
> name also aligns the naming format.

Squash it into qcs9075.dtsi.

> 
> > 
> > > 
> > > > 
> > > > > 
> > > 
> > > -- 
> > > With best wishes
> > > Dmitry
> > 
> > Regards,
> > Wasim
> 
> -- 
> Regards,
> Wasim

-- 
With best wishes
Dmitry

Re: [PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Wasim Nazir]

On Sat, Jun 07, 2025 at 11:22:39PM +0300, Dmitry Baryshkov wrote:
> On Fri, Jun 06, 2025 at 02:02:50PM +0530, Wasim Nazir wrote:
> > On Wed, Jun 04, 2025 at 09:54:38PM +0530, Wasim Nazir wrote:
> > > On Wed, Jun 04, 2025 at 04:21:46PM +0300, Dmitry Baryshkov wrote:
> > > > On Wed, Jun 04, 2025 at 03:05:55PM +0530, Wasim Nazir wrote:
> > > > > On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote:
> > > > > > On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote:
> > > > > > > From: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > > > > 
> > > > > > > SA8775P has a memory map which caters to the auto specific requirements.
> > > > > > 
> > > > > > I thought SA8775P was the IoT platform and SA8255P was the automotive
> > > > > > one. Has this changed?
> > > > > 
> > > > > Both SA8775P & SA8255P is for auto but former one is non-SCMI based while
> > > > > the later one is SCMI based chip.
> > > > > 
> > > > > Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT.
> > > > > 
> > > > > > 
> > > > > > > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
> > > > > > > inherit the memory map of SA8775P require a slightly different memory
> > > > > > > map as compared to SA8775P auto parts.
> > > > > > > This new memory map is applicable for all the IoT boards which inherit
> > > > > > > the initial SA8775P memory map. This is not applicable for non-IoT
> > > > > > 
> > > > > > Is there are platform out there that actually uses the "initial SA8775P
> > > > > > memory map"?
> > > > > 
> > > > > Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory
> > > > > map.
> > > > > 
> > > > > > 
> > > > > > > boards.
> > > > > > > 
> > > > > > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
> > > > > > > introduced as part of firmware updates for IoT. The size and base address
> > > > > > > have been updated for video PIL carveout compared to SA8775P since it is
> > > > > > > being brought up for the first time on IoT boards. The base addresses
> > > > > > > of the rest of the PIL carveouts have been updated to accommodate the
> > > > > > > change in size of video since PIL regions are relocatable and their
> > > > > > > functionality is not impacted due to this change. The size of camera
> > > > > > > pil has also been increased without breaking any feature.
> > > > > > > 
> > > > > > > The size of trusted apps carveout has also been reduced since it is
> > > > > > > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
> > > > > > > carveout and its corresponding scm reference has been removed as these
> > > > > > > are not required for IoT parts.
> > > > > > > 
> > > > > > > Incorporate these changes in the updated memory map.
> > > > > > > 
> > > > > > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > > > > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
> > > > > > > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > > > > > > ---
> > > > > > >  .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
> > > > > > >  1 file changed, 113 insertions(+)
> > > > > > >  create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > > > 
> > > > > > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > > > new file mode 100644
> > > > > > > index 000000000000..ff2600eb5e3d
> > > > > > > --- /dev/null
> > > > > > > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > > 
> > > > > > The naming convention is <soc>-<something>.dtsi and I don't see any
> > > > > > other uses of the "iq9" naming.
> > > > > 
> > > > > As this new memory map is common for IQ9 series of SoC (QCS9100 &
> > > > > QCS9075), so we have used its common name.
> > > > 
> > > > IQ9 name is not known or visible outside of this commit.
> > > 
> > > Are you referring to add the same in cover-letter?
> > > 
> > > > 
> > > > > Once the DT structure for QCS9100 is refactored, we would update this
> > > > > common file there.
> > > > 
> > > > Can you refactor it first?
> > > 
> > > This refactoring involves changes in all the ride/ride-r3 boards which
> > > are based on sa8775p & qcs9100. Even though we had sent v0[1] but we still
> > > need to conclude on the final structure. Since, ethernet is broken in upstream,
> > > we are working on its fix before sending another series.
> > > 
> > > Hence, we want to proceed for iq9075-evk for now and once qcs9100 is
> > > finalized, we can use the memory-map there.
> > > 
> > > But to avoid this dependency and to proceed with iq9075-evk alone,
> > > I can rename it to qcs9075-reserved-memory.dtsi.
> > > 
> > > Let me know if that works here.
> > > 
> > > [1] https://lore.kernel.org/all/20250507065116.353114-1-quic_wasimn@quicinc.com/
> > 
> > Hi Dmitry,
> > 
> > Shall I proceed with qcs9075-reserved-memory.dtsi or do you have any
> > other suggestion that we should discuss?
> > 
> > Aparently, this series is for qcs9075 only so using exact (not common)
> > name also aligns the naming format.
> 
> Squash it into qcs9075.dtsi.

We don't have qcs9075.dtsi.
Is it ok to squash it into qcs9075-som.dtsi ?

> 
> > 
> > > 
> > > > 
> > > > > 
> > > > > > 
> > > > 
> > > > -- 
> > > > With best wishes
> > > > Dmitry
> > > 
> > > Regards,
> > > Wasim
> > 
> > -- 
> > Regards,
> > Wasim
> 
> -- 
> With best wishes
> Dmitry

-- 
Regards,
Wasim

Re: [PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Dmitry Baryshkov]

On 09/06/2025 12:54, Wasim Nazir wrote:
> On Sat, Jun 07, 2025 at 11:22:39PM +0300, Dmitry Baryshkov wrote:
>> On Fri, Jun 06, 2025 at 02:02:50PM +0530, Wasim Nazir wrote:
>>> On Wed, Jun 04, 2025 at 09:54:38PM +0530, Wasim Nazir wrote:
>>>> On Wed, Jun 04, 2025 at 04:21:46PM +0300, Dmitry Baryshkov wrote:
>>>>> On Wed, Jun 04, 2025 at 03:05:55PM +0530, Wasim Nazir wrote:
>>>>>> On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote:
>>>>>>> On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote:
>>>>>>>> From: Pratyush Brahma <quic_pbrahma@quicinc.com>
>>>>>>>>
>>>>>>>> SA8775P has a memory map which caters to the auto specific requirements.
>>>>>>>
>>>>>>> I thought SA8775P was the IoT platform and SA8255P was the automotive
>>>>>>> one. Has this changed?
>>>>>>
>>>>>> Both SA8775P & SA8255P is for auto but former one is non-SCMI based while
>>>>>> the later one is SCMI based chip.
>>>>>>
>>>>>> Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT.
>>>>>>
>>>>>>>
>>>>>>>> QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
>>>>>>>> inherit the memory map of SA8775P require a slightly different memory
>>>>>>>> map as compared to SA8775P auto parts.
>>>>>>>> This new memory map is applicable for all the IoT boards which inherit
>>>>>>>> the initial SA8775P memory map. This is not applicable for non-IoT
>>>>>>>
>>>>>>> Is there are platform out there that actually uses the "initial SA8775P
>>>>>>> memory map"?
>>>>>>
>>>>>> Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory
>>>>>> map.
>>>>>>
>>>>>>>
>>>>>>>> boards.
>>>>>>>>
>>>>>>>> Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
>>>>>>>> introduced as part of firmware updates for IoT. The size and base address
>>>>>>>> have been updated for video PIL carveout compared to SA8775P since it is
>>>>>>>> being brought up for the first time on IoT boards. The base addresses
>>>>>>>> of the rest of the PIL carveouts have been updated to accommodate the
>>>>>>>> change in size of video since PIL regions are relocatable and their
>>>>>>>> functionality is not impacted due to this change. The size of camera
>>>>>>>> pil has also been increased without breaking any feature.
>>>>>>>>
>>>>>>>> The size of trusted apps carveout has also been reduced since it is
>>>>>>>> sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
>>>>>>>> carveout and its corresponding scm reference has been removed as these
>>>>>>>> are not required for IoT parts.
>>>>>>>>
>>>>>>>> Incorporate these changes in the updated memory map.
>>>>>>>>
>>>>>>>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
>>>>>>>> Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
>>>>>>>> Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
>>>>>>>> ---
>>>>>>>>   .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
>>>>>>>>   1 file changed, 113 insertions(+)
>>>>>>>>   create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
>>>>>>>> new file mode 100644
>>>>>>>> index 000000000000..ff2600eb5e3d
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
>>>>>>>
>>>>>>> The naming convention is <soc>-<something>.dtsi and I don't see any
>>>>>>> other uses of the "iq9" naming.
>>>>>>
>>>>>> As this new memory map is common for IQ9 series of SoC (QCS9100 &
>>>>>> QCS9075), so we have used its common name.
>>>>>
>>>>> IQ9 name is not known or visible outside of this commit.
>>>>
>>>> Are you referring to add the same in cover-letter?
>>>>
>>>>>
>>>>>> Once the DT structure for QCS9100 is refactored, we would update this
>>>>>> common file there.
>>>>>
>>>>> Can you refactor it first?
>>>>
>>>> This refactoring involves changes in all the ride/ride-r3 boards which
>>>> are based on sa8775p & qcs9100. Even though we had sent v0[1] but we still
>>>> need to conclude on the final structure. Since, ethernet is broken in upstream,
>>>> we are working on its fix before sending another series.
>>>>
>>>> Hence, we want to proceed for iq9075-evk for now and once qcs9100 is
>>>> finalized, we can use the memory-map there.
>>>>
>>>> But to avoid this dependency and to proceed with iq9075-evk alone,
>>>> I can rename it to qcs9075-reserved-memory.dtsi.
>>>>
>>>> Let me know if that works here.
>>>>
>>>> [1] https://lore.kernel.org/all/20250507065116.353114-1-quic_wasimn@quicinc.com/
>>>
>>> Hi Dmitry,
>>>
>>> Shall I proceed with qcs9075-reserved-memory.dtsi or do you have any
>>> other suggestion that we should discuss?
>>>
>>> Aparently, this series is for qcs9075 only so using exact (not common)
>>> name also aligns the naming format.
>>
>> Squash it into qcs9075.dtsi.
> 
> We don't have qcs9075.dtsi.
> Is it ok to squash it into qcs9075-som.dtsi ?

Is the memory map specific to SoM or to the SoC?

> 
>>
>>>
>>>>
>>>>>
>>>>>>
>>>>>>>
>>>>>
>>>>> -- 
>>>>> With best wishes
>>>>> Dmitry
>>>>
>>>> Regards,
>>>> Wasim
>>>
>>> -- 
>>> Regards,
>>> Wasim
>>
>> -- 
>> With best wishes
>> Dmitry
> 


-- 
With best wishes
Dmitry

Re: [PATCH v9 2/4] arm64: dts: qcom: iq9: Introduce new memory map for qcs9100/qcs9075

[Wasim Nazir]

On Mon, Jun 09, 2025 at 01:03:02PM +0300, Dmitry Baryshkov wrote:
> On 09/06/2025 12:54, Wasim Nazir wrote:
> > On Sat, Jun 07, 2025 at 11:22:39PM +0300, Dmitry Baryshkov wrote:
> > > On Fri, Jun 06, 2025 at 02:02:50PM +0530, Wasim Nazir wrote:
> > > > On Wed, Jun 04, 2025 at 09:54:38PM +0530, Wasim Nazir wrote:
> > > > > On Wed, Jun 04, 2025 at 04:21:46PM +0300, Dmitry Baryshkov wrote:
> > > > > > On Wed, Jun 04, 2025 at 03:05:55PM +0530, Wasim Nazir wrote:
> > > > > > > On Mon, Jun 02, 2025 at 10:41:39AM -0500, Bjorn Andersson wrote:
> > > > > > > > On Fri, May 30, 2025 at 02:58:45PM +0530, Wasim Nazir wrote:
> > > > > > > > > From: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > > > > > > 
> > > > > > > > > SA8775P has a memory map which caters to the auto specific requirements.
> > > > > > > > 
> > > > > > > > I thought SA8775P was the IoT platform and SA8255P was the automotive
> > > > > > > > one. Has this changed?
> > > > > > > 
> > > > > > > Both SA8775P & SA8255P is for auto but former one is non-SCMI based while
> > > > > > > the later one is SCMI based chip.
> > > > > > > 
> > > > > > > Only IQ9 series of chips (QCS9100 & QCS9075) are for IOT.
> > > > > > > 
> > > > > > > > 
> > > > > > > > > QCS9100 & QCS9075 are its IOT variants (with marketing name as IQ9) which
> > > > > > > > > inherit the memory map of SA8775P require a slightly different memory
> > > > > > > > > map as compared to SA8775P auto parts.
> > > > > > > > > This new memory map is applicable for all the IoT boards which inherit
> > > > > > > > > the initial SA8775P memory map. This is not applicable for non-IoT
> > > > > > > > 
> > > > > > > > Is there are platform out there that actually uses the "initial SA8775P
> > > > > > > > memory map"?
> > > > > > > 
> > > > > > > Yes currently sa8775p-ride and sa8775p-ride-r3 are using initial memory
> > > > > > > map.
> > > > > > > 
> > > > > > > > 
> > > > > > > > > boards.
> > > > > > > > > 
> > > > > > > > > Some new carveouts (viz. gunyah_md and a few pil dtb carveouts) have been
> > > > > > > > > introduced as part of firmware updates for IoT. The size and base address
> > > > > > > > > have been updated for video PIL carveout compared to SA8775P since it is
> > > > > > > > > being brought up for the first time on IoT boards. The base addresses
> > > > > > > > > of the rest of the PIL carveouts have been updated to accommodate the
> > > > > > > > > change in size of video since PIL regions are relocatable and their
> > > > > > > > > functionality is not impacted due to this change. The size of camera
> > > > > > > > > pil has also been increased without breaking any feature.
> > > > > > > > > 
> > > > > > > > > The size of trusted apps carveout has also been reduced since it is
> > > > > > > > > sufficient to meet IoT requirements. Also, audio_mdf_mem & tz_ffi_mem
> > > > > > > > > carveout and its corresponding scm reference has been removed as these
> > > > > > > > > are not required for IoT parts.
> > > > > > > > > 
> > > > > > > > > Incorporate these changes in the updated memory map.
> > > > > > > > > 
> > > > > > > > > Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> > > > > > > > > Signed-off-by: Prakash Gupta <quic_guptap@quicinc.com>
> > > > > > > > > Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com>
> > > > > > > > > ---
> > > > > > > > >   .../boot/dts/qcom/iq9-reserved-memory.dtsi    | 113 ++++++++++++++++++
> > > > > > > > >   1 file changed, 113 insertions(+)
> > > > > > > > >   create mode 100644 arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > > > > > 
> > > > > > > > > diff --git a/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > > > > > new file mode 100644
> > > > > > > > > index 000000000000..ff2600eb5e3d
> > > > > > > > > --- /dev/null
> > > > > > > > > +++ b/arch/arm64/boot/dts/qcom/iq9-reserved-memory.dtsi
> > > > > > > > 
> > > > > > > > The naming convention is <soc>-<something>.dtsi and I don't see any
> > > > > > > > other uses of the "iq9" naming.
> > > > > > > 
> > > > > > > As this new memory map is common for IQ9 series of SoC (QCS9100 &
> > > > > > > QCS9075), so we have used its common name.
> > > > > > 
> > > > > > IQ9 name is not known or visible outside of this commit.
> > > > > 
> > > > > Are you referring to add the same in cover-letter?
> > > > > 
> > > > > > 
> > > > > > > Once the DT structure for QCS9100 is refactored, we would update this
> > > > > > > common file there.
> > > > > > 
> > > > > > Can you refactor it first?
> > > > > 
> > > > > This refactoring involves changes in all the ride/ride-r3 boards which
> > > > > are based on sa8775p & qcs9100. Even though we had sent v0[1] but we still
> > > > > need to conclude on the final structure. Since, ethernet is broken in upstream,
> > > > > we are working on its fix before sending another series.
> > > > > 
> > > > > Hence, we want to proceed for iq9075-evk for now and once qcs9100 is
> > > > > finalized, we can use the memory-map there.
> > > > > 
> > > > > But to avoid this dependency and to proceed with iq9075-evk alone,
> > > > > I can rename it to qcs9075-reserved-memory.dtsi.
> > > > > 
> > > > > Let me know if that works here.
> > > > > 
> > > > > [1] https://lore.kernel.org/all/20250507065116.353114-1-quic_wasimn@quicinc.com/
> > > > 
> > > > Hi Dmitry,
> > > > 
> > > > Shall I proceed with qcs9075-reserved-memory.dtsi or do you have any
> > > > other suggestion that we should discuss?
> > > > 
> > > > Aparently, this series is for qcs9075 only so using exact (not common)
> > > > name also aligns the naming format.
> > > 
> > > Squash it into qcs9075.dtsi.
> > 
> > We don't have qcs9075.dtsi.
> > Is it ok to squash it into qcs9075-som.dtsi ?
> 
> Is the memory map specific to SoM or to the SoC?

Understood, will create soc file and add the memory map changes.

> 
> > 
> > > 
> > > > 
> > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > 
> > > > > > -- 
> > > > > > With best wishes
> > > > > > Dmitry
> > > > > 
> > > > > Regards,
> > > > > Wasim
> > > > 
> > > > -- 
> > > > Regards,
> > > > Wasim
> > > 
> > > -- 
> > > With best wishes
> > > Dmitry
> > 
> 
> 
> -- 
> With best wishes
> Dmitry

-- 
Regards,
Wasim