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To: "Langsdorf, Mark" <mark.langsdorf@amd.com>
Cc: "Len Brown" <lenb@kernel.org>,
       "Linus Torvalds" <torvalds@linux-foundation.org>,
       "Morrow, William" <William.Morrow@amd.com>,
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Subject: Re: [PATCH] i386: add command line option "local_apic_timer_c2_ok"
References: <Pine.LNX.4.64.0703160925270.26106@woody.linux-foundation.org>
	<Pine.LNX.4.64.0703271430310.6730@woody.linux-foundation.org>
	<200703271816.33868.lenb@kernel.org>
	<200703272218.50531.lenb@kernel.org>
	<1449F58C868D8D4E9C72945771150BDFD967BB@SAUSEXMB1.amd.com>
From: Andi Kleen <andi@firstfloor.org>
Date: 29 Mar 2007 18:50:09 +0200
In-Reply-To: <1449F58C868D8D4E9C72945771150BDFD967BB@SAUSEXMB1.amd.com>
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"Langsdorf, Mark" <mark.langsdorf@amd.com> writes:

> > > If we really care about using the LAPIC timer on systems with deeper
> > > than C1 support, the only alternative seems to be to test
> > > if it actually works or not at boot and run-time.
> > > Otherwise, we wait for future hardware with guaranteed
> > > not to break under any (BIOS) conditions ships, and check for that.
> > > 
> > > Based on what I read of the HP nx6325 where the LAPIC timer
> > > is breaking C1, AMD is in the same boat.
> > 
> > The nx6325 (Turion 64 X2) exports only C1.
> > I'm not sure how the conclusion was drawn that it has
> > a broken lapic timer as reflected in the "nolapic_timer" patch:
> 
> If both cores goes into C1 at the same time, the chipset
> can move the processor into a C3 like state called C1e.

... and that seems to break the local APIC timer.

> AMD can craft a patch to sort this out as soon as we have
> an idea what the framework is going to look like.

Just a snippet to detect it would be great. Then the dmi scan
could be removed and replaced with that. This would be a 2.6.21
candidate imho over the DMI hack.

-Andi