From: Andi Kleen <andi@firstfloor.org>
To: Jesse Barnes <jesse.barnes@intel.com>
Cc: "Dr. David Alan Gilbert" <linux@treblig.org>,
linux-kernel@vger.kernel.org
Subject: Re: Intel Memory Ordering White Paper
Date: 19 Sep 2007 19:29:44 +0200 [thread overview]
Message-ID: <p73k5qmva0n.fsf@bingen.suse.de> (raw)
In-Reply-To: <200709190926.55200.jesse.barnes@intel.com>
Jesse Barnes <jesse.barnes@intel.com> writes:
>
> It's really both (1) and (2). This document will become part of the
> regular manuals when the next version is published. And yes,
> processors may do something different internally, but software can rely
> on the behavior described by the rules in the document.
... until the first erratum comes around. With the multitude of x86
cores being introduced all the time (how many did only Intel just announce at
IDF?@) that is going to happen sooner or later.
i386 with full legacy enabled already has to care about old PPros and
those seriously violate write ordering.
-Andi
prev parent reply other threads:[~2007-09-19 17:30 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-09-07 22:26 Intel Memory Ordering White Paper Jesse Barnes
2007-09-08 8:54 ` Nick Piggin
2007-09-07 23:20 ` Linus Torvalds
2007-09-08 17:34 ` Nick Piggin
2007-09-08 17:48 ` Nick Piggin
2007-09-07 18:13 ` Nick Piggin
2007-09-08 8:53 ` Andi Kleen
2007-09-07 19:57 ` Nick Piggin
2007-09-08 10:19 ` Andi Kleen
2007-09-07 20:32 ` Nick Piggin
2007-09-08 20:37 ` H. Peter Anvin
2007-09-08 11:34 ` dean gaudet
2007-09-08 12:08 ` Petr Vandrovec
2007-09-08 12:27 ` dean gaudet
2007-09-08 10:30 ` Alan Cox
2007-09-07 20:46 ` Nick Piggin
2007-09-08 10:29 ` Alan Cox
2007-09-07 20:49 ` Nick Piggin
2007-09-08 14:11 ` Alan Cox
2007-09-12 18:26 ` Dr. David Alan Gilbert
2007-09-19 16:26 ` Jesse Barnes
2007-09-19 17:29 ` Andi Kleen [this message]
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