From: Andi Kleen <ak@suse.de>
To: Adrian Bunk <bunk@fs.tum.de>
Cc: marcelo.tosatti@cyclades.com.br, linux-kernel@vger.kernel.org
Subject: Re: [2.4 patch] fix CONFIG_X86_L1_CACHE_SHIFT
Date: 07 Sep 2003 22:30:52 +0200 [thread overview]
Message-ID: <p73u17ojq83.fsf@oldwotan.suse.de> (raw)
In-Reply-To: <20030907195557.GK14436@fs.tum.de.suse.lists.linux.kernel>
Adrian Bunk <bunk@fs.tum.de> writes:
> With CONFIG_M686 CONFIG_X86_L1_CACHE_SHIFT was set to 5, but a Pentium 4
> requires 7.
It doesn't require 7, it just prefers 7.
> The patch below does:
> - set CONFIG_X86_L1_CACHE_SHIFT 7 for all Intel processors (needed for
> the Pentium 4)
> - set CONFIG_X86_L1_CACHE_SHIFT 6 for the K6 (needed for the Athlon)
I think these changes should be only done with CONFIG_X86_GENERIC is set.
Otherwise the people who want kernels really optimized for their CPUs
won't get the full benefit. On UP it does not make that much difference,
but on a SMP kernel having a bigger than needed cache size wastes a lot
of memory.
-Andi
next parent reply other threads:[~2003-09-07 20:31 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20030907195557.GK14436@fs.tum.de.suse.lists.linux.kernel>
2003-09-07 20:30 ` Andi Kleen [this message]
2003-09-07 21:39 ` [2.4 patch] fix CONFIG_X86_L1_CACHE_SHIFT Dave Jones
2003-09-08 8:15 ` Peter Daum
[not found] ` <Pine.LNX.4.30.0309072228110.9987-100000@swamp.bayern.net.suse.lists.linux.kernel>
2003-09-07 21:57 ` Andi Kleen
2003-09-07 20:36 Manfred Spraul
2003-09-08 14:20 ` Adrian Bunk
2003-09-08 17:07 ` Jamie Lokier
2003-09-08 17:24 ` Jeff Garzik
2003-09-08 19:45 ` Manfred Spraul
2003-09-09 14:49 ` Peter Daum
-- strict thread matches above, loose matches on Subject: below --
2003-09-07 19:55 Adrian Bunk
2003-09-07 20:59 ` Peter Daum
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