From: Andi Kleen <ak@suse.de>
To: Daniel J Blueman <daniel.blueman@gmail.com>
Cc: linux-kernel@vger.kernel.org, jgarzik@pobox.com
Subject: Re: PAT status?
Date: 30 Nov 2005 14:58:20 -0700 [thread overview]
Message-ID: <p73zmnlg5mr.fsf@verdi.suse.de> (raw)
In-Reply-To: <6278d2220511300404i27878f02mf5d8c948256d36e8@mail.gmail.com>
Daniel J Blueman <daniel.blueman@gmail.com> writes:
> IIRC, the kernel (c. 2.6.14) still does nothing to setup the
> processors' PAT registers to enable write combining in one of the
> slots - the defaults the BIOS establishes do not cover this. Once this
> is done, drivers would readily be able to set page flags for a
> particular PAT slot, and MTRRs can (almost) be safely ignored.
As usual when something hasn't been done yet it's not that easy...
Problem is that they would very likely create very subtle problems
by creating conflicting mappings with the different cache attributes,
which leads to cache corruption and other nasty issues.
That is why more infrastructure is needed in the kernel to do this
properly.
-Andi
next prev parent reply other threads:[~2005-11-30 17:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-11-30 12:04 PAT status? Daniel J Blueman
2005-11-30 21:58 ` Andi Kleen [this message]
2005-12-01 14:30 ` Daniel J Blueman
-- strict thread matches above, loose matches on Subject: below --
2005-12-08 15:37 Daniel J Blueman
2005-12-09 18:45 ` Dave Jones
2005-11-29 22:22 Jeff Garzik
2005-12-01 20:49 ` Terence Ripperda
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