From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5DCBC10F12 for ; Wed, 17 Apr 2019 09:21:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ADD6121773 for ; Wed, 17 Apr 2019 09:21:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731630AbfDQJVw (ORCPT ); Wed, 17 Apr 2019 05:21:52 -0400 Received: from mx2.suse.de ([195.135.220.15]:49280 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731611AbfDQJVu (ORCPT ); Wed, 17 Apr 2019 05:21:50 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id BC4E4B143; Wed, 17 Apr 2019 09:21:49 +0000 (UTC) Date: Wed, 17 Apr 2019 11:21:48 +0200 Message-ID: From: Takashi Iwai To: Cc: , , , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: Re: [ALSA patch] [PATCH] ALSA: pcm: Enable MMAP status and control for ARMv7 and ARMv8 In-Reply-To: <1555490771-13242-1-git-send-email-twischer@de.adit-jv.com> References: <1555490771-13242-1-git-send-email-twischer@de.adit-jv.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 Emacs/25.3 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 17 Apr 2019 10:46:11 +0200, wrote: > > From: Timo Wischer > > Since ARMv7 hardware cache coherence is supported. > "The SCU maintains coherency between the individual data caches in the > Cortex-A5 MPCore processor using a variation of the MOESI protocol" [1]. > > Therefore this patch enables the MMAP access to the status and control > structures. This avoids HWSYYNC ioctl calls and therefore lowers the CPU > usage. > > [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0434c/ > BABJECBF.html Interesting... I thought it would never work properly on ARM. If it really works like that, I'd happily apply the change. But I'd like to hear a confirmation from ARM people before merging such an intensive change. thanks, Takashi > > Signed-off-by: Timo Wischer > --- > sound/core/pcm_native.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c > index 1d84529..b8019ef 100644 > --- a/sound/core/pcm_native.c > +++ b/sound/core/pcm_native.c > @@ -3225,7 +3225,8 @@ static __poll_t snd_pcm_poll(struct file *file, poll_table *wait) > * Only on coherent architectures, we can mmap the status and the control records > * for effcient data transfer. On others, we have to use HWSYNC ioctl... > */ > -#if defined(CONFIG_X86) || defined(CONFIG_PPC) || defined(CONFIG_ALPHA) > +#if defined(CONFIG_X86) || defined(CONFIG_PPC) || defined(CONFIG_ALPHA) || \ > + (defined(CONFIG_ARM) && defined(CONFIG_CPU_V7)) || defined(CONFIG_ARM64) > /* > * mmap status record > */ > -- > 2.7.4 > > _______________________________________________ > Patch mailing list > Patch@alsa-project.org > https://mailman.alsa-project.org/mailman/listinfo/patch >