From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752783AbcAFSvg (ORCPT ); Wed, 6 Jan 2016 13:51:36 -0500 Received: from terminus.zytor.com ([198.137.202.10]:54750 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752073AbcAFSvb (ORCPT ); Wed, 6 Jan 2016 13:51:31 -0500 Date: Wed, 6 Jan 2016 10:50:50 -0800 From: tip-bot for Andi Kleen Message-ID: Cc: tglx@linutronix.de, mingo@kernel.org, jolsa@redhat.com, acme@redhat.com, hpa@zytor.com, vincent.weaver@maine.edu, peterz@infradead.org, eranian@google.com, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, ak@linux.intel.com Reply-To: torvalds@linux-foundation.org, ak@linux.intel.com, linux-kernel@vger.kernel.org, vincent.weaver@maine.edu, peterz@infradead.org, eranian@google.com, hpa@zytor.com, acme@redhat.com, jolsa@redhat.com, mingo@kernel.org, tglx@linutronix.de In-Reply-To: <1449177740-5422-2-git-send-email-andi@firstfloor.org> References: <1449177740-5422-2-git-send-email-andi@firstfloor.org> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86: Allow zero PEBS status with only single active event Git-Commit-ID: 01330d7288e0050c5aaabc558059ff91589e67cd X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 01330d7288e0050c5aaabc558059ff91589e67cd Gitweb: http://git.kernel.org/tip/01330d7288e0050c5aaabc558059ff91589e67cd Author: Andi Kleen AuthorDate: Thu, 3 Dec 2015 13:22:20 -0800 Committer: Ingo Molnar CommitDate: Wed, 6 Jan 2016 11:15:31 +0100 perf/x86: Allow zero PEBS status with only single active event Normally we drop PEBS events with a zero status field. But when there is only a single PEBS event active we can assume the PEBS record is for that event. The PEBS buffer is always flushed when PEBS events are disabled, so there is no risk of mishandling state PEBS records this way. Signed-off-by: Andi Kleen Signed-off-by: Peter Zijlstra (Intel) Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Link: http://lkml.kernel.org/r/1449177740-5422-2-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event_intel_ds.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 0e3a9c7..cd1993e 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -1230,6 +1230,18 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) pebs_status = p->status & cpuc->pebs_enabled; pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1; + /* + * On some CPUs the PEBS status can be zero when PEBS is + * racing with clearing of GLOBAL_STATUS. + * + * Normally we would drop that record, but in the + * case when there is only a single active PEBS event + * we can assume it's for that event. + */ + if (!pebs_status && cpuc->pebs_enabled && + !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) + pebs_status = cpuc->pebs_enabled; + bit = find_first_bit((unsigned long *)&pebs_status, x86_pmu.max_pebs_events); if (bit >= x86_pmu.max_pebs_events)