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From: tip-bot for Konrad Rzeszutek Wilk <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: konrad.wilk@oracle.com, dwmw@amazon.co.uk, mingo@kernel.org,
	tglx@linutronix.de, hpa@zytor.com, bp@suse.de,
	keescook@chromium.org, linux-kernel@vger.kernel.org,
	karahmed@amazon.de
Subject: [tip:x86/pti] x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features
Date: Wed, 6 Jun 2018 05:16:53 -0700	[thread overview]
Message-ID: <tip-108fab4b5c8f12064ef86e02cb0459992affb30f@git.kernel.org> (raw)
In-Reply-To: <20180601145921.9500-4-konrad.wilk@oracle.com>

Commit-ID:  108fab4b5c8f12064ef86e02cb0459992affb30f
Gitweb:     https://git.kernel.org/tip/108fab4b5c8f12064ef86e02cb0459992affb30f
Author:     Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
AuthorDate: Fri, 1 Jun 2018 10:59:21 -0400
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 6 Jun 2018 14:13:17 +0200

x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features

Both AMD and Intel can have SPEC_CTRL_MSR for SSBD.

However AMD also has two more other ways of doing it - which
are !SPEC_CTRL MSR ways.

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Kees Cook <keescook@chromium.org>
Cc: kvm@vger.kernel.org
Cc: KarimAllah Ahmed <karahmed@amazon.de>
Cc: andrew.cooper3@citrix.com
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: David Woodhouse <dwmw@amazon.co.uk>
Link: https://lkml.kernel.org/r/20180601145921.9500-4-konrad.wilk@oracle.com

---
 arch/x86/kernel/cpu/bugs.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 6bea81855cdd..cd0fda1fff6d 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -532,17 +532,12 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
 		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
 		 * use a completely different MSR and bit dependent on family.
 		 */
-		switch (boot_cpu_data.x86_vendor) {
-		case X86_VENDOR_INTEL:
-		case X86_VENDOR_AMD:
-			if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
-				x86_amd_ssb_disable();
-				break;
-			}
+		if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
+			x86_amd_ssb_disable();
+		else {
 			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
 			x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
 			wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
-			break;
 		}
 	}
 

  reply	other threads:[~2018-06-06 12:17 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-01 14:59 [PATCH v1] AMD SSB bits Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 1/3] x86/bugs: Add AMD's variant of SSB_NO Konrad Rzeszutek Wilk
2018-06-06 12:15   ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 2/3] x86/bugs: Add AMD's SPEC_CTRL MSR usage Konrad Rzeszutek Wilk
2018-06-02  1:04   ` Tom Lendacky
2018-06-04 20:20     ` Konrad Rzeszutek Wilk
2018-06-04 20:43       ` Tom Lendacky
2018-06-04 20:54         ` Konrad Rzeszutek Wilk
2018-06-06 12:16   ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 3/3] x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features Konrad Rzeszutek Wilk
2018-06-06 12:16   ` tip-bot for Konrad Rzeszutek Wilk [this message]
2018-06-08 21:30   ` Tom Lendacky
2018-06-11 14:01     ` Konrad Rzeszutek Wilk
2018-06-12 14:38       ` Tom Lendacky
2018-06-15 18:57         ` Thomas Gleixner
2018-06-15 19:38           ` Konrad Rzeszutek Wilk
2018-06-05 13:23 ` [PATCH v1] AMD SSB bits Tom Lendacky
2018-06-05 20:56   ` Konrad Rzeszutek Wilk

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