[PATCH] x86, realmode: fix no cache bits test in reboot_32.S

[PATCH] x86, realmode: fix no cache bits test in reboot_32.S

[Jarkko Sakkinen]

Before the new real-mode code infrastructure %edx was
used for testing CD and NW bits with andl in order to
decide whether to flush the processor caches or not.
The value of cr0 was also stored in %eax, which was
later used to set cr0 after masking out lower byte
(except TS bit) in order to enter real-mode.

In the new real-mode code infrastructure we wanted to
keep input parameter in %eax so we are using %edx for
both cr0 cases. This has caused regression since andl
overwrites the value of %edx.

This patch fixes the issue by replacing andl with testl,
which is essentially andl without writing result to the
register.

Special thanks to Paolo Bonzini for noting this and
proposing a fix.

Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@intel.com>
---
 arch/x86/realmode/rm/reboot_32.S |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/realmode/rm/reboot_32.S b/arch/x86/realmode/rm/reboot_32.S
index 8d9bfd1..1140448 100644
--- a/arch/x86/realmode/rm/reboot_32.S
+++ b/arch/x86/realmode/rm/reboot_32.S
@@ -76,7 +76,7 @@ machine_real_restart_asm16:
 	movl	%edx, %cr0
 	movl	%ecx, %cr3
 	movl	%cr0, %edx
-	andl	$0x60000000, %edx	/* If no cache bits -> no wbinvd */
+	testl	$0x60000000, %edx	/* If no cache bits -> no wbinvd */
 	jz	2f
 	wbinvd
 2:
-- 
1.7.9.5

[tip:x86/trampoline] x86, realmode: Fix no cache bits test in reboot_32.S

[tip-bot for Jarkko Sakkinen]

Commit-ID:  34d0b02e08470c56a411ba6da1f377bc6da02826
Gitweb:     http://git.kernel.org/tip/34d0b02e08470c56a411ba6da1f377bc6da02826
Author:     Jarkko Sakkinen <jarkko.sakkinen@intel.com>
AuthorDate: Thu, 10 May 2012 10:11:38 +0300
Committer:  H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Thu, 10 May 2012 19:31:22 -0700

x86, realmode: Fix no cache bits test in reboot_32.S

Before the new real-mode code infrastructure %edx was
used for testing CD and NW bits with andl in order to
decide whether to flush the processor caches or not.
The value of cr0 was also stored in %eax, which was
later used to set cr0 after masking out lower byte
(except TS bit) in order to enter real-mode.

In the new real-mode code infrastructure we wanted to
keep input parameter in %eax so we are using %edx for
both cr0 cases. This has caused regression since andl
overwrites the value of %edx.

This patch fixes the issue by replacing andl with testl,
which is essentially andl without writing result to the
register.

Special thanks to Paolo Bonzini for noting this and
proposing a fix.

Reported-and-tested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@intel.com>
Link: http://lkml.kernel.org/r/1336633898-23743-1-git-send-email-jarkko.sakkinen@intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
 arch/x86/realmode/rm/reboot_32.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/realmode/rm/reboot_32.S b/arch/x86/realmode/rm/reboot_32.S
index 8d9bfd1..1140448 100644
--- a/arch/x86/realmode/rm/reboot_32.S
+++ b/arch/x86/realmode/rm/reboot_32.S
@@ -76,7 +76,7 @@ machine_real_restart_asm16:
 	movl	%edx, %cr0
 	movl	%ecx, %cr3
 	movl	%cr0, %edx
-	andl	$0x60000000, %edx	/* If no cache bits -> no wbinvd */
+	testl	$0x60000000, %edx	/* If no cache bits -> no wbinvd */
 	jz	2f
 	wbinvd
 2: