[tip:locking/core] x86,locking: Enable qrwlock

[tip:locking/core] x86,locking: Enable qrwlock

[tip-bot for Waiman Long]

Commit-ID:  19a3e44df0600750c69d6fdffe7cb26eb3c2cfd5
Gitweb:     http://git.kernel.org/tip/19a3e44df0600750c69d6fdffe7cb26eb3c2cfd5
Author:     Waiman Long <Waiman.Long@hp.com>
AuthorDate: Mon, 3 Feb 2014 13:18:57 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 19 May 2014 22:06:01 +0900

x86,locking: Enable qrwlock

Make x86 use the fair rwlock_t.

Implement the custom queue_write_unlock() for best performance.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "Paul E.McKenney" <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Waiman Long <Waiman.Long@hp.com>
[peterz: near complete rewrite]
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/n/tip-r1xuzmdysvuhl3h86n5fbxi7@git.kernel.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/Kconfig                      |  1 +
 arch/x86/include/asm/paravirt_types.h |  7 +------
 arch/x86/include/asm/qrwlock.h        | 17 +++++++++++++++++
 arch/x86/include/asm/spinlock.h       |  4 ++++
 arch/x86/include/asm/spinlock_types.h |  4 ++++
 5 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 25d2c6f..bf7626f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -121,6 +121,7 @@ config X86
 	select MODULES_USE_ELF_RELA if X86_64
 	select CLONE_BACKWARDS if X86_32
 	select ARCH_USE_BUILTIN_BSWAP
+	select ARCH_USE_QUEUE_RWLOCK
 	select OLD_SIGSUSPEND3 if X86_32 || IA32_EMULATION
 	select OLD_SIGACTION if X86_32
 	select COMPAT_OLD_SIGACTION if IA32_EMULATION
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index 7549b8b..3d9c6be 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -326,12 +326,7 @@ struct pv_mmu_ops {
 			   phys_addr_t phys, pgprot_t flags);
 };
 
-struct arch_spinlock;
-#ifdef CONFIG_SMP
-#include <asm/spinlock_types.h>
-#else
-typedef u16 __ticket_t;
-#endif
+#include <linux/spinlock_types.h>
 
 struct pv_lock_ops {
 	struct paravirt_callee_save lock_spinning;
diff --git a/arch/x86/include/asm/qrwlock.h b/arch/x86/include/asm/qrwlock.h
new file mode 100644
index 0000000..70f46f0
--- /dev/null
+++ b/arch/x86/include/asm/qrwlock.h
@@ -0,0 +1,17 @@
+#ifndef _ASM_X86_QRWLOCK_H
+#define _ASM_X86_QRWLOCK_H
+
+#include <asm-generic/qrwlock_types.h>
+
+#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
+#define queue_write_unlock queue_write_unlock
+static inline void queue_write_unlock(struct qrwlock *lock)
+{
+        barrier();
+        ACCESS_ONCE(*(u8 *)&lock->cnts) = 0;
+}
+#endif
+
+#include <asm-generic/qrwlock.h>
+
+#endif /* _ASM_X86_QRWLOCK_H */
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index 0f62f54..54f1c80 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -187,6 +187,7 @@ static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
 		cpu_relax();
 }
 
+#ifndef CONFIG_QUEUE_RWLOCK
 /*
  * Read-write spinlocks, allowing multiple readers
  * but only one writer.
@@ -269,6 +270,9 @@ static inline void arch_write_unlock(arch_rwlock_t *rw)
 	asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0"
 		     : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory");
 }
+#else
+#include <asm/qrwlock.h>
+#endif /* CONFIG_QUEUE_RWLOCK */
 
 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
diff --git a/arch/x86/include/asm/spinlock_types.h b/arch/x86/include/asm/spinlock_types.h
index 4f1bea1..73c4c00 100644
--- a/arch/x86/include/asm/spinlock_types.h
+++ b/arch/x86/include/asm/spinlock_types.h
@@ -34,6 +34,10 @@ typedef struct arch_spinlock {
 
 #define __ARCH_SPIN_LOCK_UNLOCKED	{ { 0 } }
 
+#ifdef CONFIG_QUEUE_RWLOCK
+#include <asm-generic/qrwlock_types.h>
+#else
 #include <asm/rwlock.h>
+#endif
 
 #endif /* _ASM_X86_SPINLOCK_TYPES_H */

Re: [tip:locking/core] x86, locking/rwlocks: Enable qrwlocks on x86

[Paul Bolle]

On Fri, 2014-06-06 at 05:20 -0700, tip-bot for Waiman Long wrote:
> Make x86 use the fair rwlock_t.
> 
> Implement the custom queue_write_unlock() for best performance.

This landed in linux-next yesterday (ie, next-20140610).

> Signed-off-by: Waiman Long <Waiman.Long@hp.com>
> [peterz: near complete rewrite]
> Signed-off-by: Peter Zijlstra <peterz@infradead.org>
> Cc: Dave Jones <davej@redhat.com>
> Cc: Jeremy Fitzhardinge <jeremy@goop.org>
> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
> Cc: Linus Torvalds <torvalds@linux-foundation.org>
> Cc: Oleg Nesterov <oleg@redhat.com>
> Cc: Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com>
> Cc: "Paul E.McKenney" <paulmck@linux.vnet.ibm.com>
> Cc: linux-kernel@vger.kernel.org
> Cc: x86@kernel.org
> Link: http://lkml.kernel.org/n/tip-r1xuzmdysvuhl3h86n5fbxi7@git.kernel.org
> Signed-off-by: Ingo Molnar <mingo@kernel.org>
>[...]
> diff --git a/arch/x86/include/asm/qrwlock.h b/arch/x86/include/asm/qrwlock.h
> new file mode 100644
> index 0000000..70f46f0
> --- /dev/null
> +++ b/arch/x86/include/asm/qrwlock.h
> @@ -0,0 +1,17 @@
> +#ifndef _ASM_X86_QRWLOCK_H
> +#define _ASM_X86_QRWLOCK_H
> +
> +#include <asm-generic/qrwlock_types.h>
> +
> +#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)

X86_OOSTORE was removed in v3.14, see commit 09df7c4c8097 ("x86: Remove
CONFIG_X86_OOSTORE"). So the first test can be removed here, as it will
always be true. Should I submit the trivial, but probably untested,
patch to do that or do you prefer to do that yourself?

> +#define queue_write_unlock queue_write_unlock
> +static inline void queue_write_unlock(struct qrwlock *lock)
> +{
> +        barrier();
> +        ACCESS_ONCE(*(u8 *)&lock->cnts) = 0;
> +}
> +#endif
> +
> +#include <asm-generic/qrwlock.h>
> +
> +#endif /* _ASM_X86_QRWLOCK_H */

Thanks,


Paul Bolle

Re: [tip:locking/core] x86, locking/rwlocks: Enable qrwlocks on x86

[Peter Zijlstra]

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On Wed, Jun 11, 2014 at 10:14:11AM +0200, Paul Bolle wrote:
> On Fri, 2014-06-06 at 05:20 -0700, tip-bot for Waiman Long wrote:
> > +#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
> 
> X86_OOSTORE was removed in v3.14, see commit 09df7c4c8097 ("x86: Remove
> CONFIG_X86_OOSTORE"). So the first test can be removed here, as it will
> always be true. Should I submit the trivial, but probably untested,
> patch to do that or do you prefer to do that yourself?

I was completely unaware of that removal. Yeah, I'll queue patch
removing this new instance of it.

Good to have it gone though, one little crazy less.

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Re: [tip:locking/core] x86, locking/rwlocks: Enable qrwlocks on x86

[Peter Zijlstra]

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On Wed, Jun 11, 2014 at 10:59:21AM +0200, Peter Zijlstra wrote:
> On Wed, Jun 11, 2014 at 10:14:11AM +0200, Paul Bolle wrote:
> > On Fri, 2014-06-06 at 05:20 -0700, tip-bot for Waiman Long wrote:
> > > +#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
> > 
> > X86_OOSTORE was removed in v3.14, see commit 09df7c4c8097 ("x86: Remove
> > CONFIG_X86_OOSTORE"). So the first test can be removed here, as it will
> > always be true. Should I submit the trivial, but probably untested,
> > patch to do that or do you prefer to do that yourself?
> 
> I was completely unaware of that removal. Yeah, I'll queue patch
> removing this new instance of it.
> 
> Good to have it gone though, one little crazy less.

I've queued the below. Thanks!

---
Subject: x86, locking: No more OOSTORE nonsense
From: Peter Zijlstra <peterz@infradead.org>
Date: Wed Jun 11 11:01:45 CEST 2014

Paul reported that X86_OOSTORE is dead, yay! Update a comment and
remove a newly added reference.

Reported-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/n/tip-6w40duqjdmo3sslxtvisuh7w@git.kernel.org
---
 arch/x86/include/asm/barrier.h |    2 +-
 arch/x86/include/asm/qrwlock.h |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -99,7 +99,7 @@
 #if defined(CONFIG_X86_PPRO_FENCE)
 
 /*
- * For either of these options x86 doesn't have a strong TSO memory
+ * For this option x86 doesn't have a strong TSO memory
  * model and we should fall back to full barriers.
  */
 
--- a/arch/x86/include/asm/qrwlock.h
+++ b/arch/x86/include/asm/qrwlock.h
@@ -3,7 +3,7 @@
 
 #include <asm-generic/qrwlock_types.h>
 
-#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
+#ifndef CONFIG_X86_PPRO_FENCE
 #define queue_write_unlock queue_write_unlock
 static inline void queue_write_unlock(struct qrwlock *lock)
 {



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[tip:locking/core] x86, locking: Use no more OOSTORE nonsense

[tip-bot for Peter Zijlstra]

Commit-ID:  4f3aaf2c2ba35bc2cd823a240f9969ebfb3c7549
Gitweb:     http://git.kernel.org/tip/4f3aaf2c2ba35bc2cd823a240f9969ebfb3c7549
Author:     Peter Zijlstra <peterz@infradead.org>
AuthorDate: Wed, 11 Jun 2014 11:01:45 +0200
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Wed, 18 Jun 2014 18:41:22 +0200

x86, locking: Use no more OOSTORE nonsense

Paul reported that X86_OOSTORE is dead, yay! Update a comment and
remove a newly added reference.

Reported-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Dave Jones <davej@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Waiman Long <Waiman.Long@hp.com>
Cc: Will Deacon <will.deacon@arm.com>
Link: http://lkml.kernel.org/r/20140611090509.GC3588@twins.programming.kicks-ass.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/include/asm/barrier.h | 2 +-
 arch/x86/include/asm/qrwlock.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
index 5c7198c..0f4460b 100644
--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -99,7 +99,7 @@
 #if defined(CONFIG_X86_PPRO_FENCE)
 
 /*
- * For either of these options x86 doesn't have a strong TSO memory
+ * For this option x86 doesn't have a strong TSO memory
  * model and we should fall back to full barriers.
  */
 
diff --git a/arch/x86/include/asm/qrwlock.h b/arch/x86/include/asm/qrwlock.h
index 70f46f0..ae0e241 100644
--- a/arch/x86/include/asm/qrwlock.h
+++ b/arch/x86/include/asm/qrwlock.h
@@ -3,7 +3,7 @@
 
 #include <asm-generic/qrwlock_types.h>
 
-#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
+#ifndef CONFIG_X86_PPRO_FENCE
 #define queue_write_unlock queue_write_unlock
 static inline void queue_write_unlock(struct qrwlock *lock)
 {