From: tip-bot for Stephane Eranian <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: acme@redhat.com, peterz@infradead.org,
torvalds@linux-foundation.org, mingo@kernel.org,
alexander.shishkin@linux.intel.com, stable@vger.kernel.org,
hpa@zytor.com, eranian@google.com, jolsa@redhat.com,
linux-kernel@vger.kernel.org, tglx@linutronix.de,
vincent.weaver@maine.edu
Subject: [tip:perf/core] perf/x86/intel: Add definition for PT PMI bit
Date: Tue, 8 Mar 2016 05:16:07 -0800 [thread overview]
Message-ID: <tip-5690ae28e472d25e330ad0c637a5cea3fc39fb32@git.kernel.org> (raw)
In-Reply-To: <1457034642-21837-2-git-send-email-eranian@google.com>
Commit-ID: 5690ae28e472d25e330ad0c637a5cea3fc39fb32
Gitweb: http://git.kernel.org/tip/5690ae28e472d25e330ad0c637a5cea3fc39fb32
Author: Stephane Eranian <eranian@google.com>
AuthorDate: Thu, 3 Mar 2016 20:50:40 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 8 Mar 2016 12:18:34 +0100
perf/x86/intel: Add definition for PT PMI bit
This patch adds a definition for GLOBAL_OVFL_STATUS bit 55
which is used with the Processor Trace (PT) feature.
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: <stable@vger.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: adrian.hunter@intel.com
Cc: kan.liang@intel.com
Cc: namhyung@kernel.org
Link: http://lkml.kernel.org/r/1457034642-21837-2-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/perf_event.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 7bcb861..5a2ed3e 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -165,6 +165,7 @@ struct x86_pmu_capability {
#define GLOBAL_STATUS_ASIF BIT_ULL(60)
#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58)
+#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(55)
/*
* IBS cpuid feature detection
next prev parent reply other threads:[~2016-03-08 13:17 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-03 19:50 [PATCH 0/3] perf/x86/pebs: various important fixes for PEBS Stephane Eranian
2016-03-03 19:50 ` [PATCH 1/3] perf/x86/intel: add definition for PT PMI bit Stephane Eranian
2016-03-08 13:16 ` tip-bot for Stephane Eranian [this message]
2016-03-03 19:50 ` [PATCH 2/3] perf/x86/pebs: add workaround for broken OVFL status on HSW Stephane Eranian
2016-03-03 21:43 ` Andi Kleen
2016-03-03 23:40 ` Stephane Eranian
2016-03-07 10:24 ` Peter Zijlstra
2016-03-07 12:18 ` Peter Zijlstra
2016-03-07 18:27 ` Jiri Olsa
2016-03-07 20:25 ` Peter Zijlstra
2016-03-08 20:59 ` Stephane Eranian
2016-03-08 21:07 ` Peter Zijlstra
2016-03-08 21:13 ` Stephane Eranian
2016-03-09 5:34 ` Stephane Eranian
2016-03-09 5:44 ` Stephane Eranian
2016-03-09 17:40 ` Stephane Eranian
2016-03-10 10:42 ` Peter Zijlstra
2016-12-14 17:55 ` Peter Zijlstra
2016-12-15 7:26 ` Stephane Eranian
2016-12-15 7:52 ` Jiri Olsa
2016-12-15 8:04 ` Stephane Eranian
2016-12-15 8:42 ` Peter Zijlstra
2016-12-15 16:59 ` Stephane Eranian
2016-12-15 17:10 ` Peter Zijlstra
2016-12-16 8:38 ` Stephane Eranian
2016-12-16 17:48 ` Stephane Eranian
2016-03-10 13:53 ` Peter Zijlstra
2016-03-10 16:10 ` Stephane Eranian
2016-03-08 13:16 ` [tip:perf/core] perf/x86/pebs: Add workaround for broken OVFL status on HSW+ tip-bot for Stephane Eranian
2016-03-03 19:50 ` [PATCH 3/3] perf/x86/pebs: add proper PEBS constraints for Broadwell Stephane Eranian
2016-03-08 13:16 ` [tip:perf/core] perf/x86/pebs: Add " tip-bot for Stephane Eranian
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