From: tip-bot for Aravind Gopalakrishnan <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: tony.luck@intel.com, mingo@kernel.org,
linux-kernel@vger.kernel.org, tglx@linutronix.de,
linux-edac@vger.kernel.org, peterz@infradead.org, bp@alien8.de,
Aravind.Gopalakrishnan@amd.com, hpa@zytor.com,
torvalds@linux-foundation.org, bp@suse.de
Subject: [tip:ras/core] x86/mce/AMD: Reduce number of blocks scanned per bank
Date: Mon, 1 Feb 2016 03:41:12 -0800 [thread overview]
Message-ID: <tip-60f116fca162d9488f783f5014779463243ab7a2@git.kernel.org> (raw)
In-Reply-To: <1453750913-4781-6-git-send-email-bp@alien8.de>
Commit-ID: 60f116fca162d9488f783f5014779463243ab7a2
Gitweb: http://git.kernel.org/tip/60f116fca162d9488f783f5014779463243ab7a2
Author: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
AuthorDate: Mon, 25 Jan 2016 20:41:50 +0100
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 1 Feb 2016 10:53:57 +0100
x86/mce/AMD: Reduce number of blocks scanned per bank
>From Fam17h onwards, the number of extended MCx_MISC register blocks is
reduced to 4. It is an architectural change from what we had on
earlier processors.
Although theoritically the total number of extended MCx_MISC
registers was 8 in earlier processor families, in practice we
only had to use the extra registers for MC4. And only 2 of those
were used. So this change does not affect older processors.
Tested on Fam10h and Fam15h systems.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1453750913-4781-6-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 3068ce2..5982227 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -28,7 +28,7 @@
#include <asm/msr.h>
#include <asm/trace/irq_vectors.h>
-#define NR_BLOCKS 9
+#define NR_BLOCKS 5
#define THRESHOLD_MAX 0xFFF
#define INT_TYPE_APIC 0x00020000
#define MASK_VALID_HI 0x80000000
next prev parent reply other threads:[~2016-02-01 11:42 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-25 19:41 [PATCH 0/8] tip-queue 2016-01-25 Borislav Petkov
2016-01-25 19:41 ` [PATCH 1/8] x86/traps.c: Refactor preemption and interrupt flag handling Borislav Petkov
2016-02-01 11:39 ` [tip:x86/asm] x86/entry/traps: " tip-bot for Alexander Kuleshov
2016-01-25 19:41 ` [PATCH 2/8] x86/cpufeature: Use enum cpuid_leafs instead of magic numbers Borislav Petkov
2016-02-01 11:40 ` [tip:x86/cpu] " tip-bot for Huaitong Han
2016-01-25 19:41 ` [PATCH 3/8] x86/mce: Fix order of AMD MCE init function call Borislav Petkov
2016-02-01 11:40 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 4/8] x86/mce/AMD: Do not perform shared bank check for future processors Borislav Petkov
2016-02-01 11:40 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 5/8] x86/mce/AMD: Reduce number of blocks scanned per bank Borislav Petkov
2016-02-01 11:41 ` tip-bot for Aravind Gopalakrishnan [this message]
2016-01-25 19:41 ` [PATCH 6/8] x86/mce/AMD: Fix LVT offset configuration for thresholding Borislav Petkov
2016-02-01 11:41 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
2016-01-25 19:41 ` [PATCH 7/8] x86/mce/AMD: Carve out threshold block preparation Borislav Petkov
2016-02-01 11:41 ` [tip:ras/core] " tip-bot for Borislav Petkov
2016-01-25 19:41 ` [PATCH 8/8] x86/mce/AMD: Set MCAX Enable bit Borislav Petkov
2016-02-01 11:42 ` [tip:ras/core] " tip-bot for Aravind Gopalakrishnan
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