From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757781AbcEFJyx (ORCPT ); Fri, 6 May 2016 05:54:53 -0400 Received: from terminus.zytor.com ([198.137.202.10]:46872 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751511AbcEFJyw (ORCPT ); Fri, 6 May 2016 05:54:52 -0400 Date: Fri, 6 May 2016 02:54:38 -0700 From: tip-bot for Chen Yu Message-ID: Cc: yu.c.chen@intel.com, mingo@kernel.org, rafael@kernel.org, bin.gao@intel.com, lenb@kernel.org, tglx@linutronix.de, linux-kernel@vger.kernel.org, hpa@zytor.com Reply-To: rafael@kernel.org, yu.c.chen@intel.com, mingo@kernel.org, linux-kernel@vger.kernel.org, hpa@zytor.com, lenb@kernel.org, bin.gao@intel.com, tglx@linutronix.de In-Reply-To: <1462505619-5516-1-git-send-email-yu.c.chen@intel.com> References: <1462505619-5516-1-git-send-email-yu.c.chen@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/urgent] x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO Git-Commit-ID: 886123fb3a8656699dff40afa0573df359abeb18 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 886123fb3a8656699dff40afa0573df359abeb18 Gitweb: http://git.kernel.org/tip/886123fb3a8656699dff40afa0573df359abeb18 Author: Chen Yu AuthorDate: Fri, 6 May 2016 11:33:39 +0800 Committer: Thomas Gleixner CommitDate: Fri, 6 May 2016 11:50:50 +0200 x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO Currently we read the tsc radio: ratio = (MSR_PLATFORM_INFO >> 8) & 0x1f; Thus we get bit 8-12 of MSR_PLATFORM_INFO, however according to the SDM (35.5), the ratio bits are bit 8-15. Ignoring the upper bits can result in an incorrect tsc ratio, which causes the TSC calibration and the Local APIC timer frequency to be incorrect. Fix this problem by masking 0xff instead. [ tglx: Massaged changelog ] Fixes: 7da7c1561366 "x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCs" Signed-off-by: Chen Yu Cc: "Rafael J. Wysocki" Cc: stable@vger.kernel.org Cc: Bin Gao Cc: Len Brown Link: http://lkml.kernel.org/r/1462505619-5516-1-git-send-email-yu.c.chen@intel.com Signed-off-by: Thomas Gleixner --- arch/x86/kernel/tsc_msr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c index 92ae6ac..6aa0f4d 100644 --- a/arch/x86/kernel/tsc_msr.c +++ b/arch/x86/kernel/tsc_msr.c @@ -92,7 +92,7 @@ unsigned long try_msr_calibrate_tsc(void) if (freq_desc_tables[cpu_index].msr_plat) { rdmsr(MSR_PLATFORM_INFO, lo, hi); - ratio = (lo >> 8) & 0x1f; + ratio = (lo >> 8) & 0xff; } else { rdmsr(MSR_IA32_PERF_STATUS, lo, hi); ratio = (hi >> 8) & 0x1f;