From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933060AbbHIKZo (ORCPT ); Sun, 9 Aug 2015 06:25:44 -0400 Received: from terminus.zytor.com ([198.137.202.10]:36107 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932956AbbHIKZj (ORCPT ); Sun, 9 Aug 2015 06:25:39 -0400 Date: Sun, 9 Aug 2015 03:25:00 -0700 From: "tip-bot for Jonathan (Zhixiong) Zhang" Message-ID: Cc: matt.fleming@intel.com, tglx@linutronix.de, zjzhang@codeaurora.org, linux-kernel@vger.kernel.org, mingo@kernel.org, catalin.marinas@arm.com, peterz@infradead.org, hpa@zytor.com, torvalds@linux-foundation.org Reply-To: tglx@linutronix.de, matt.fleming@intel.com, zjzhang@codeaurora.org, catalin.marinas@arm.com, mingo@kernel.org, peterz@infradead.org, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, hpa@zytor.com In-Reply-To: <1438936621-5215-6-git-send-email-matt@codeblueprint.co.uk> References: <1438936621-5215-6-git-send-email-matt@codeblueprint.co.uk> To: linux-tip-commits@vger.kernel.org Subject: [tip:core/efi] arm64/mm: Add PROT_DEVICE_nGnRnE and PROT_NORMAL_WT Git-Commit-ID: 8d446c8647c9ab8fcb45a8fc7dbbafe1f83aa2f3 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 8d446c8647c9ab8fcb45a8fc7dbbafe1f83aa2f3 Gitweb: http://git.kernel.org/tip/8d446c8647c9ab8fcb45a8fc7dbbafe1f83aa2f3 Author: Jonathan (Zhixiong) Zhang AuthorDate: Fri, 7 Aug 2015 09:36:59 +0100 Committer: Ingo Molnar CommitDate: Sat, 8 Aug 2015 10:37:40 +0200 arm64/mm: Add PROT_DEVICE_nGnRnE and PROT_NORMAL_WT UEFI spec 2.5 section 2.3.6.1 defines that EFI_MEMORY_[UC|WC|WT|WB] are possible EFI memory types for AArch64. Each of those EFI memory types is mapped to a corresponding AArch64 memory type. So we need to define PROT_DEVICE_nGnRnE and PROT_NORMWL_WT additionaly. MT_NORMAL_WT is defined, and its encoding is added to MAIR_EL1 when initializing the CPU. Signed-off-by: Jonathan (Zhixiong) Zhang Signed-off-by: Matt Fleming Reviewed-by: Catalin Marinas Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/1438936621-5215-6-git-send-email-matt@codeblueprint.co.uk Signed-off-by: Ingo Molnar --- arch/arm64/include/asm/memory.h | 1 + arch/arm64/include/asm/pgtable.h | 2 ++ arch/arm64/mm/proc.S | 4 +++- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index f800d45..4112b3d 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -100,6 +100,7 @@ #define MT_DEVICE_GRE 2 #define MT_NORMAL_NC 3 #define MT_NORMAL 4 +#define MT_NORMAL_WT 5 /* * Memory types for Stage-2 translation diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 56283f8..0a105e3 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -61,8 +61,10 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF) #endif +#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRnE)) #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC)) +#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_WT)) #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL)) #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 39139a3..160a1b5 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -167,12 +167,14 @@ ENTRY(__cpu_setup) * DEVICE_GRE 010 00001100 * NORMAL_NC 011 01000100 * NORMAL 100 11111111 + * NORMAL_WT 101 10111011 */ ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ MAIR(0x04, MT_DEVICE_nGnRE) | \ MAIR(0x0c, MT_DEVICE_GRE) | \ MAIR(0x44, MT_NORMAL_NC) | \ - MAIR(0xff, MT_NORMAL) + MAIR(0xff, MT_NORMAL) | \ + MAIR(0xbb, MT_NORMAL_WT) msr mair_el1, x5 /* * Prepare SCTLR