* [PATCH 1/2] x86/AVX-512: AVX-512 Feature Detection
@ 2014-02-20 21:24 Fenghua Yu
2014-02-20 21:24 ` [PATCH 2/2] x86/AVX-512: Enable AVX-512 States Context Switch Fenghua Yu
2014-02-20 22:19 ` [tip:x86/cpufeature] x86, AVX-512: AVX-512 Feature Detection tip-bot for Fenghua Yu
0 siblings, 2 replies; 4+ messages in thread
From: Fenghua Yu @ 2014-02-20 21:24 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Asit K Mallick
Cc: linux-kernel, x86, Fenghua Yu
From: Fenghua Yu <fenghua.yu@intel.com>
AVX-512 is an extention of AVX2. Its spec can be found at:
http://download-software.intel.com/sites/default/files/managed/71/2e/319433-017.pdf
This patch detects AVX-512 features by CPUID.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
arch/x86/include/asm/cpufeature.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index e099f95..5f12968 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -217,9 +217,13 @@
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
+#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */
#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
+#define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */
+#define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */
+#define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */
/*
* BUG word(s)
--
1.8.1.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] x86/AVX-512: Enable AVX-512 States Context Switch
2014-02-20 21:24 [PATCH 1/2] x86/AVX-512: AVX-512 Feature Detection Fenghua Yu
@ 2014-02-20 21:24 ` Fenghua Yu
2014-02-20 22:19 ` [tip:x86/cpufeature] x86, AVX-512: " tip-bot for Fenghua Yu
2014-02-20 22:19 ` [tip:x86/cpufeature] x86, AVX-512: AVX-512 Feature Detection tip-bot for Fenghua Yu
1 sibling, 1 reply; 4+ messages in thread
From: Fenghua Yu @ 2014-02-20 21:24 UTC (permalink / raw)
To: Ingo Molnar, H. Peter Anvin, Thomas Gleixner, Asit K Mallick
Cc: linux-kernel, x86, Fenghua Yu
From: Fenghua Yu <fenghua.yu@intel.com>
This patch enables Opmask, ZMM_Hi256, and Hi16_ZMM AVX-512 states for
xstate context switch.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
arch/x86/include/asm/xsave.h | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 5547389..82173f6 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -6,11 +6,14 @@
#define XSTATE_CPUID 0x0000000d
-#define XSTATE_FP 0x1
-#define XSTATE_SSE 0x2
-#define XSTATE_YMM 0x4
-#define XSTATE_BNDREGS 0x8
-#define XSTATE_BNDCSR 0x10
+#define XSTATE_FP 0x1
+#define XSTATE_SSE 0x2
+#define XSTATE_YMM 0x4
+#define XSTATE_BNDREGS 0x8
+#define XSTATE_BNDCSR 0x10
+#define XSTATE_OPMASK 0x20
+#define XSTATE_ZMM_Hi256 0x40
+#define XSTATE_Hi16_ZMM 0x80
#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
@@ -23,7 +26,8 @@
#define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
/* Supported features which support lazy state saving */
-#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM \
+ | XSTATE_OPMASK | XSTATE_ZMM_Hi256 | XSTATE_Hi16_ZMM)
/* Supported features which require eager state saving */
#define XSTATE_EAGER (XSTATE_BNDREGS | XSTATE_BNDCSR)
--
1.8.1.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [tip:x86/cpufeature] x86, AVX-512: AVX-512 Feature Detection
2014-02-20 21:24 [PATCH 1/2] x86/AVX-512: AVX-512 Feature Detection Fenghua Yu
2014-02-20 21:24 ` [PATCH 2/2] x86/AVX-512: Enable AVX-512 States Context Switch Fenghua Yu
@ 2014-02-20 22:19 ` tip-bot for Fenghua Yu
1 sibling, 0 replies; 4+ messages in thread
From: tip-bot for Fenghua Yu @ 2014-02-20 22:19 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, hpa, mingo, fenghua.yu, tglx, hpa
Commit-ID: 8e5780fdeef7dc490b3f0b3a62704593721fa4f3
Gitweb: http://git.kernel.org/tip/8e5780fdeef7dc490b3f0b3a62704593721fa4f3
Author: Fenghua Yu <fenghua.yu@intel.com>
AuthorDate: Thu, 20 Feb 2014 13:24:50 -0800
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Thu, 20 Feb 2014 13:56:55 -0800
x86, AVX-512: AVX-512 Feature Detection
AVX-512 is an extention of AVX2. Its spec can be found at:
http://download-software.intel.com/sites/default/files/managed/71/2e/319433-017.pdf
This patch detects AVX-512 features by CPUID.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Link: http://lkml.kernel.org/r/1392931491-33237-1-git-send-email-fenghua.yu@intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cc: <stable@vger.kernel.org> # hw enabling
---
arch/x86/include/asm/cpufeature.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index e099f95..5f12968 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -217,9 +217,13 @@
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
+#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */
#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
+#define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */
+#define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */
+#define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */
/*
* BUG word(s)
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [tip:x86/cpufeature] x86, AVX-512: Enable AVX-512 States Context Switch
2014-02-20 21:24 ` [PATCH 2/2] x86/AVX-512: Enable AVX-512 States Context Switch Fenghua Yu
@ 2014-02-20 22:19 ` tip-bot for Fenghua Yu
0 siblings, 0 replies; 4+ messages in thread
From: tip-bot for Fenghua Yu @ 2014-02-20 22:19 UTC (permalink / raw)
To: linux-tip-commits; +Cc: linux-kernel, hpa, mingo, fenghua.yu, tglx, hpa
Commit-ID: c2bc11f10a39527cd1bb252097b5525664560956
Gitweb: http://git.kernel.org/tip/c2bc11f10a39527cd1bb252097b5525664560956
Author: Fenghua Yu <fenghua.yu@intel.com>
AuthorDate: Thu, 20 Feb 2014 13:24:51 -0800
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Thu, 20 Feb 2014 13:56:55 -0800
x86, AVX-512: Enable AVX-512 States Context Switch
This patch enables Opmask, ZMM_Hi256, and Hi16_ZMM AVX-512 states for
xstate context switch.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Link: http://lkml.kernel.org/r/1392931491-33237-2-git-send-email-fenghua.yu@intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cc: <stable@vger.kernel.org> # hw enabling
---
arch/x86/include/asm/xsave.h | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 5547389..6c1d741 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -6,11 +6,14 @@
#define XSTATE_CPUID 0x0000000d
-#define XSTATE_FP 0x1
-#define XSTATE_SSE 0x2
-#define XSTATE_YMM 0x4
-#define XSTATE_BNDREGS 0x8
-#define XSTATE_BNDCSR 0x10
+#define XSTATE_FP 0x1
+#define XSTATE_SSE 0x2
+#define XSTATE_YMM 0x4
+#define XSTATE_BNDREGS 0x8
+#define XSTATE_BNDCSR 0x10
+#define XSTATE_OPMASK 0x20
+#define XSTATE_ZMM_Hi256 0x40
+#define XSTATE_Hi16_ZMM 0x80
#define XSTATE_FPSSE (XSTATE_FP | XSTATE_SSE)
@@ -23,7 +26,8 @@
#define XSAVE_YMM_OFFSET (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
/* Supported features which support lazy state saving */
-#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM \
+ | XSTATE_OPMASK | XSTATE_ZMM_Hi256 | XSTATE_Hi16_ZMM)
/* Supported features which require eager state saving */
#define XSTATE_EAGER (XSTATE_BNDREGS | XSTATE_BNDCSR)
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-02-20 22:19 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-02-20 21:24 [PATCH 1/2] x86/AVX-512: AVX-512 Feature Detection Fenghua Yu
2014-02-20 21:24 ` [PATCH 2/2] x86/AVX-512: Enable AVX-512 States Context Switch Fenghua Yu
2014-02-20 22:19 ` [tip:x86/cpufeature] x86, AVX-512: " tip-bot for Fenghua Yu
2014-02-20 22:19 ` [tip:x86/cpufeature] x86, AVX-512: AVX-512 Feature Detection tip-bot for Fenghua Yu
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox