From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964779AbcFCKvt (ORCPT ); Fri, 3 Jun 2016 06:51:49 -0400 Received: from terminus.zytor.com ([198.137.202.10]:56222 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932149AbcFCKvr (ORCPT ); Fri, 3 Jun 2016 06:51:47 -0400 Date: Fri, 3 Jun 2016 03:51:04 -0700 From: tip-bot for Lukasz Odzioba Message-ID: Cc: eranian@google.com, ak@linux.intel.com, mingo@kernel.org, alexander.shishkin@linux.intel.com, torvalds@linux-foundation.org, peterz@infradead.org, tglx@linutronix.de, linux-kernel@vger.kernel.org, jolsa@redhat.com, vincent.weaver@maine.edu, lukasz.odzioba@intel.com, acme@redhat.com, hpa@zytor.com Reply-To: hpa@zytor.com, acme@redhat.com, lukasz.odzioba@intel.com, vincent.weaver@maine.edu, jolsa@redhat.com, linux-kernel@vger.kernel.org, tglx@linutronix.de, peterz@infradead.org, torvalds@linux-foundation.org, alexander.shishkin@linux.intel.com, mingo@kernel.org, ak@linux.intel.com, eranian@google.com In-Reply-To: <1463433419-16893-1-git-send-email-lukasz.odzioba@intel.com> References: <1463433419-16893-1-git-send-email-lukasz.odzioba@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel: Change offcore response masks for Knights Landing Git-Commit-ID: 9c489fce7a4a46c8a408e16e126bf3225401c7b5 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 9c489fce7a4a46c8a408e16e126bf3225401c7b5 Gitweb: http://git.kernel.org/tip/9c489fce7a4a46c8a408e16e126bf3225401c7b5 Author: Lukasz Odzioba AuthorDate: Mon, 16 May 2016 23:16:59 +0200 Committer: Ingo Molnar CommitDate: Fri, 3 Jun 2016 09:40:17 +0200 perf/x86/intel: Change offcore response masks for Knights Landing Due to change in register definition we need to update OCR mask: MSR_OFFCORE_RESP0 reserved bits: 3,4,18,29,30,33,34, 8,11,14 MSR_OFFCORE_RESP1 reserved bits: 3,4,18,29,30,33,34, 38 Reported-by: Andi Kleen Signed-off-by: Lukasz Odzioba Signed-off-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Cc: akpm@linux-foundation.org Cc: hpa@zytor.com Cc: kan.liang@intel.com Cc: lukasz.anaczkowski@intel.com Cc: zheng.z.yan@intel.com Link: http://lkml.kernel.org/r/1463433419-16893-1-git-send-email-lukasz.odzioba@intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/core.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index ad08caf..0941f84 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -186,10 +186,8 @@ static struct event_constraint intel_skl_event_constraints[] = { }; static struct extra_reg intel_knl_extra_regs[] __read_mostly = { - INTEL_UEVENT_EXTRA_REG(0x01b7, - MSR_OFFCORE_RSP_0, 0x7f9ffbffffull, RSP_0), - INTEL_UEVENT_EXTRA_REG(0x02b7, - MSR_OFFCORE_RSP_1, 0x3f9ffbffffull, RSP_1), + INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0), + INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1), EVENT_EXTRA_END };