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From: tip-bot for Andre Przywara <andre.przywara@amd.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@redhat.com,
	andre.przywara@amd.com, tglx@linutronix.de, hpa@linux.intel.com
Subject: [tip:x86/cpu] x86, kvm: add new AMD SVM feature bits
Date: Wed, 8 Sep 2010 21:28:49 GMT	[thread overview]
Message-ID: <tip-aeb9c7d618264dcf6eea39142fefee096c3b09e2@git.kernel.org> (raw)
In-Reply-To: <1283778860-26843-5-git-send-email-andre.przywara@amd.com>

Commit-ID:  aeb9c7d618264dcf6eea39142fefee096c3b09e2
Gitweb:     http://git.kernel.org/tip/aeb9c7d618264dcf6eea39142fefee096c3b09e2
Author:     Andre Przywara <andre.przywara@amd.com>
AuthorDate: Mon, 6 Sep 2010 15:14:20 +0200
Committer:  H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Wed, 8 Sep 2010 13:34:15 -0700

x86, kvm: add new AMD SVM feature bits

The recently updated CPUID specification names new SVM feature bits.
Add them to the list of reported features.

Signed-off-by: Andre Przywara <andre.przywara@amd,com>
LKML-Reference: <1283778860-26843-5-git-send-email-andre.przywara@amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
 arch/x86/include/asm/cpufeature.h |    7 +++++++
 arch/x86/kernel/cpu/scattered.c   |    6 ++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 341835df..bffeab7 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -183,6 +183,13 @@
 #define X86_FEATURE_LBRV	(8*32+ 6) /* AMD LBR Virtualization support */
 #define X86_FEATURE_SVML	(8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
 #define X86_FEATURE_NRIPS	(8*32+ 8) /* "nrip_save" AMD SVM next_rip save */
+#define X86_FEATURE_TSCRATEMSR  (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
+#define X86_FEATURE_VMCBCLEAN   (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */
+#define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */
+#define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */
+#define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */
+#define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */
+
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
 #define X86_FEATURE_FSGSBASE	(9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 34b4dad..2c77931 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -43,6 +43,12 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
 		{ X86_FEATURE_LBRV,		CR_EDX, 1, 0x8000000a, 0 },
 		{ X86_FEATURE_SVML,		CR_EDX, 2, 0x8000000a, 0 },
 		{ X86_FEATURE_NRIPS,		CR_EDX, 3, 0x8000000a, 0 },
+		{ X86_FEATURE_TSCRATEMSR,	CR_EDX, 4, 0x8000000a, 0 },
+		{ X86_FEATURE_VMCBCLEAN,	CR_EDX, 5, 0x8000000a, 0 },
+		{ X86_FEATURE_FLUSHBYASID,	CR_EDX, 6, 0x8000000a, 0 },
+		{ X86_FEATURE_DECODEASSISTS,	CR_EDX, 7, 0x8000000a, 0 },
+		{ X86_FEATURE_PAUSEFILTER,	CR_EDX,10, 0x8000000a, 0 },
+		{ X86_FEATURE_PFTHRESHOLD,	CR_EDX,12, 0x8000000a, 0 },
 		{ 0, 0, 0, 0, 0 }
 	};
 

      reply	other threads:[~2010-09-08 21:29 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-09-06 13:14 [PATCH 0/4 -v2] x86: update AMD CPUID bits Andre Przywara
2010-09-06 13:14 ` [PATCH 1/4] x86: Fix misnamed AMD CPUID feature bit Andre Przywara
2010-09-08 21:27   ` [tip:x86/cpu] x86, cpu: Fix renamed, not-yet-shipping " tip-bot for Andre Przywara
2010-09-06 13:14 ` [PATCH 2/4] x86: Update AMD CPUID feature bits Andre Przywara
2010-09-08 21:28   ` [tip:x86/cpu] x86, cpu: " tip-bot for Andre Przywara
2010-09-06 13:14 ` [PATCH 3/4] x86: Fix allowed CPUID bits for KVM guests Andre Przywara
2010-09-06 18:47   ` Avi Kivity
2010-09-08 21:28   ` [tip:x86/cpu] x86, cpu: " tip-bot for Andre Przywara
2010-09-06 13:14 ` [PATCH 4/4] x86, kvm: add new AMD SVM feature bits Andre Przywara
2010-09-08 21:28   ` tip-bot for Andre Przywara [this message]

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