From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751906AbdGRKu2 (ORCPT ); Tue, 18 Jul 2017 06:50:28 -0400 Received: from terminus.zytor.com ([65.50.211.136]:51679 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751365AbdGRKuZ (ORCPT ); Tue, 18 Jul 2017 06:50:25 -0400 Date: Tue, 18 Jul 2017 03:44:49 -0700 From: tip-bot for Jiri Olsa Message-ID: Cc: kan.liang@intel.com, tglx@linutronix.de, torvalds@linux-foundation.org, a.p.zijlstra@chello.nl, mingo@kernel.org, jolsa@kernel.org, hpa@zytor.com, linux-kernel@vger.kernel.org, peterz@infradead.org, alexander.shishkin@linux.intel.com Reply-To: torvalds@linux-foundation.org, a.p.zijlstra@chello.nl, mingo@kernel.org, hpa@zytor.com, linux-kernel@vger.kernel.org, jolsa@kernel.org, alexander.shishkin@linux.intel.com, peterz@infradead.org, kan.liang@intel.com, tglx@linutronix.de In-Reply-To: <20170714163551.19459-1-jolsa@kernel.org> References: <20170714163551.19459-1-jolsa@kernel.org> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/urgent] perf/x86/intel: Fix debug_store reset field for freq events Git-Commit-ID: b32fd2f3f667c8a94f2f6bc2fb88a607be8f3229 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: b32fd2f3f667c8a94f2f6bc2fb88a607be8f3229 Gitweb: http://git.kernel.org/tip/b32fd2f3f667c8a94f2f6bc2fb88a607be8f3229 Author: Jiri Olsa AuthorDate: Fri, 14 Jul 2017 18:35:51 +0200 Committer: Ingo Molnar CommitDate: Tue, 18 Jul 2017 11:06:12 +0200 perf/x86/intel: Fix debug_store reset field for freq events There's a bug in PEBs event enabling code, that prevents PEBS freq events to work properly after non freq PEBS event was run. freq events - perf_event_attr::freq set -F option of perf record PEBS events - perf_event_attr::precise_ip > 0 default for perf record Like in following example with CPU 0 busy, we expect ~10000 samples for following perf tool run: # perf record -F 10000 -C 0 sleep 1 [ perf record: Woken up 2 times to write data ] [ perf record: Captured and wrote 0.640 MB perf.data (10031 samples) ] Everything's fine, but once we run non freq PEBS event like: # perf record -c 10000 -C 0 sleep 1 [ perf record: Woken up 4 times to write data ] [ perf record: Captured and wrote 1.053 MB perf.data (20061 samples) ] the freq events start to fail like this: # perf record -F 10000 -C 0 sleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.185 MB perf.data (40 samples) ] The issue is in non freq PEBs event initialization of debug_store reset field, which value is used to auto-reload the counter value after PEBS event drain. This value is not being used for PEBS freq events, but once we run non freq event it stays in debug_store data and screws the sample_freq counting for PEBS freq events. Setting the reset field to 0 for freq events. Signed-off-by: Jiri Olsa Acked-by: Peter Zijlstra (Intel) Cc: Alexander Shishkin Cc: Kan Liang Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/20170714163551.19459-1-jolsa@kernel.org Signed-off-by: Ingo Molnar --- arch/x86/events/intel/ds.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 2ca4d2d..6dc8a59 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -895,6 +895,8 @@ void intel_pmu_pebs_enable(struct perf_event *event) if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { ds->pebs_event_reset[hwc->idx] = (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; + } else { + ds->pebs_event_reset[hwc->idx] = 0; } }