From: tip-bot for Fenghua Yu <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@kernel.org,
fenghua.yu@intel.com, tglx@linutronix.de, hpa@linux.intel.com
Subject: [tip:x86/xsave] x86/xsaves: Define a macro for handling xsave/ xrstor instruction fault
Date: Fri, 30 May 2014 08:11:49 -0700 [thread overview]
Message-ID: <tip-b84e70552e5aad71a1c14536e6ffcfe7934b73e4@git.kernel.org> (raw)
In-Reply-To: <1401387164-43416-8-git-send-email-fenghua.yu@intel.com>
Commit-ID: b84e70552e5aad71a1c14536e6ffcfe7934b73e4
Gitweb: http://git.kernel.org/tip/b84e70552e5aad71a1c14536e6ffcfe7934b73e4
Author: Fenghua Yu <fenghua.yu@intel.com>
AuthorDate: Thu, 29 May 2014 11:12:35 -0700
Committer: H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Thu, 29 May 2014 14:31:18 -0700
x86/xsaves: Define a macro for handling xsave/xrstor instruction fault
Define a macro to handle fault generated by xsave, xsaveopt, xsaves, xrstor,
and xrstors instructions. It is used in functions like xsave_state() etc.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Link: http://lkml.kernel.org/r/1401387164-43416-8-git-send-email-fenghua.yu@intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
arch/x86/include/asm/xsave.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 71bdde4..76c2459 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -58,6 +58,13 @@ extern int init_fpu(struct task_struct *child);
#define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f"
#define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
+#define xstate_fault ".section .fixup,\"ax\"\n" \
+ "3: movl $-1,%[err]\n" \
+ " jmp 2b\n" \
+ ".previous\n" \
+ _ASM_EXTABLE(1b, 3b) \
+ : [err] "=r" (err)
+
static inline int fpu_xrstor_checking(struct xsave_struct *fx)
{
int err;
parent reply other threads:[~2014-05-30 15:12 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <1401387164-43416-8-git-send-email-fenghua.yu@intel.com>]
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