From: tip-bot for Jiri Olsa <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: acme@kernel.org, alexander.shishkin@linux.intel.com,
namhyung@kernel.org, torvalds@linux-foundation.org,
hpa@zytor.com, gregkh@linuxfoundation.org, tglx@linutronix.de,
peterz@infradead.org, jolsa@kernel.org,
linux-kernel@vger.kernel.org, mingo@kernel.org
Subject: [tip:perf/core] perf/x86: Use the new pmu::update_attrs attribute group
Date: Mon, 3 Jun 2019 06:27:33 -0700 [thread overview]
Message-ID: <tip-baa0c83363c7aafb04734acf4ac252be8e13bd88@git.kernel.org> (raw)
In-Reply-To: <20190512155518.21468-5-jolsa@kernel.org>
Commit-ID: baa0c83363c7aafb04734acf4ac252be8e13bd88
Gitweb: https://git.kernel.org/tip/baa0c83363c7aafb04734acf4ac252be8e13bd88
Author: Jiri Olsa <jolsa@kernel.org>
AuthorDate: Sun, 12 May 2019 17:55:13 +0200
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Mon, 3 Jun 2019 11:58:23 +0200
perf/x86: Use the new pmu::update_attrs attribute group
Using the new pmu::update_attrs attribute group to
create detected events for x86_pmu.
Moving the topdown/memory/tsx attributes to separate
attribute groups with specific is_visible functions.
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20190512155518.21468-5-jolsa@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/core.c | 10 ++----
arch/x86/events/intel/core.c | 86 +++++++++++++++++++++++++-------------------
arch/x86/events/perf_event.h | 2 +-
3 files changed, 52 insertions(+), 46 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 0c5a2c783374..db815ceb5017 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1855,14 +1855,6 @@ static int __init init_hw_perf_events(void)
else
filter_events(x86_pmu_events_group.attrs);
- if (x86_pmu.cpu_events) {
- struct attribute **tmp;
-
- tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
- if (!WARN_ON(!tmp))
- x86_pmu_events_group.attrs = tmp;
- }
-
if (x86_pmu.attrs) {
struct attribute **tmp;
@@ -1871,6 +1863,8 @@ static int __init init_hw_perf_events(void)
x86_pmu_attr_group.attrs = tmp;
}
+ pmu.attr_update = x86_pmu.attr_update;
+
pr_info("... version: %d\n", x86_pmu.version);
pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
pr_info("... generic registers: %d\n", x86_pmu.num_counters);
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index a5436cee20b1..600e87055ba9 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4274,13 +4274,6 @@ static struct attribute *icl_tsx_events_attrs[] = {
NULL,
};
-static __init struct attribute **get_icl_events_attrs(void)
-{
- return boot_cpu_has(X86_FEATURE_RTM) ?
- merge_attr(icl_events_attrs, icl_tsx_events_attrs) :
- icl_events_attrs;
-}
-
static ssize_t freeze_on_smi_show(struct device *cdev,
struct device_attribute *attr,
char *buf)
@@ -4406,32 +4399,47 @@ static struct attribute *intel_pmu_attrs[] = {
NULL,
};
-static __init struct attribute **
-get_events_attrs(struct attribute **base,
- struct attribute **mem,
- struct attribute **tsx)
+static umode_t
+tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
{
- struct attribute **attrs = base;
- struct attribute **old;
+ return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
+}
- if (mem && x86_pmu.pebs)
- attrs = merge_attr(attrs, mem);
+static umode_t
+pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
+{
+ return x86_pmu.pebs ? attr->mode : 0;
+}
- if (tsx && boot_cpu_has(X86_FEATURE_RTM)) {
- old = attrs;
- attrs = merge_attr(attrs, tsx);
- if (old != base)
- kfree(old);
- }
+static struct attribute_group group_events_td = {
+ .name = "events",
+};
- return attrs;
-}
+static struct attribute_group group_events_mem = {
+ .name = "events",
+ .is_visible = pebs_is_visible,
+};
+
+static struct attribute_group group_events_tsx = {
+ .name = "events",
+ .is_visible = tsx_is_visible,
+};
+
+static const struct attribute_group *attr_update[] = {
+ &group_events_td,
+ &group_events_mem,
+ &group_events_tsx,
+ NULL,
+};
+
+static struct attribute *empty_attrs;
__init int intel_pmu_init(void)
{
- struct attribute **extra_attr = NULL;
- struct attribute **mem_attr = NULL;
- struct attribute **tsx_attr = NULL;
+ struct attribute **extra_attr = &empty_attrs;
+ struct attribute **td_attr = &empty_attrs;
+ struct attribute **mem_attr = &empty_attrs;
+ struct attribute **tsx_attr = &empty_attrs;
struct attribute **to_free = NULL;
union cpuid10_edx edx;
union cpuid10_eax eax;
@@ -4596,7 +4604,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
x86_pmu.extra_regs = intel_slm_extra_regs;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
- x86_pmu.cpu_events = slm_events_attrs;
+ td_attr = slm_events_attrs;
extra_attr = slm_format_attr;
pr_cont("Silvermont events, ");
name = "silvermont";
@@ -4624,7 +4632,7 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_prec_dist = true;
x86_pmu.lbr_pt_coexist = true;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
- x86_pmu.cpu_events = glm_events_attrs;
+ td_attr = glm_events_attrs;
extra_attr = slm_format_attr;
pr_cont("Goldmont events, ");
name = "goldmont";
@@ -4651,7 +4659,7 @@ __init int intel_pmu_init(void)
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_PEBS_ALL;
x86_pmu.get_event_constraints = glp_get_event_constraints;
- x86_pmu.cpu_events = glm_events_attrs;
+ td_attr = glm_events_attrs;
/* Goldmont Plus has 4-wide pipeline */
event_attr_td_total_slots_scale_glm.event_str = "4";
extra_attr = slm_format_attr;
@@ -4740,7 +4748,7 @@ __init int intel_pmu_init(void)
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
- x86_pmu.cpu_events = snb_events_attrs;
+ td_attr = snb_events_attrs;
mem_attr = snb_mem_events_attrs;
/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
@@ -4781,7 +4789,7 @@ __init int intel_pmu_init(void)
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
- x86_pmu.cpu_events = snb_events_attrs;
+ td_attr = snb_events_attrs;
mem_attr = snb_mem_events_attrs;
/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
@@ -4818,10 +4826,10 @@ __init int intel_pmu_init(void)
x86_pmu.hw_config = hsw_hw_config;
x86_pmu.get_event_constraints = hsw_get_event_constraints;
- x86_pmu.cpu_events = hsw_events_attrs;
x86_pmu.lbr_double_abort = true;
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
hsw_format_attr : nhm_format_attr;
+ td_attr = hsw_events_attrs;
mem_attr = hsw_mem_events_attrs;
tsx_attr = hsw_tsx_events_attrs;
pr_cont("Haswell events, ");
@@ -4860,10 +4868,10 @@ __init int intel_pmu_init(void)
x86_pmu.hw_config = hsw_hw_config;
x86_pmu.get_event_constraints = hsw_get_event_constraints;
- x86_pmu.cpu_events = hsw_events_attrs;
x86_pmu.limit_period = bdw_limit_period;
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
hsw_format_attr : nhm_format_attr;
+ td_attr = hsw_events_attrs;
mem_attr = hsw_mem_events_attrs;
tsx_attr = hsw_tsx_events_attrs;
pr_cont("Broadwell events, ");
@@ -4922,7 +4930,7 @@ __init int intel_pmu_init(void)
hsw_format_attr : nhm_format_attr;
extra_attr = merge_attr(extra_attr, skl_format_attr);
to_free = extra_attr;
- x86_pmu.cpu_events = hsw_events_attrs;
+ td_attr = hsw_events_attrs;
mem_attr = hsw_mem_events_attrs;
tsx_attr = hsw_tsx_events_attrs;
intel_pmu_pebs_data_source_skl(
@@ -4960,7 +4968,8 @@ __init int intel_pmu_init(void)
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
hsw_format_attr : nhm_format_attr;
extra_attr = merge_attr(extra_attr, skl_format_attr);
- x86_pmu.cpu_events = get_icl_events_attrs();
+ mem_attr = icl_events_attrs;
+ tsx_attr = icl_tsx_events_attrs;
x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02);
x86_pmu.lbr_pt_coexist = true;
intel_pmu_pebs_data_source_skl(false);
@@ -4994,8 +5003,11 @@ __init int intel_pmu_init(void)
WARN_ON(!x86_pmu.format_attrs);
}
- x86_pmu.cpu_events = get_events_attrs(x86_pmu.cpu_events,
- mem_attr, tsx_attr);
+ group_events_td.attrs = td_attr;
+ group_events_mem.attrs = mem_attr;
+ group_events_tsx.attrs = tsx_attr;
+
+ x86_pmu.attr_update = attr_update;
if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 1599008f156a..629b313d8b8b 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -634,7 +634,7 @@ struct x86_pmu {
struct attribute **caps_attrs;
ssize_t (*events_sysfs_show)(char *page, u64 config);
- struct attribute **cpu_events;
+ const struct attribute_group **attr_update;
unsigned long attr_freeze_on_smi;
struct attribute **attrs;
next prev parent reply other threads:[~2019-06-03 13:27 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-12 15:55 [PATCHv2 0/9] perf/x86: Add update attribute groups Jiri Olsa
2019-05-12 15:55 ` [PATCH 1/9] sysfs: Add sysfs_update_groups function Jiri Olsa
2019-06-03 13:25 ` [tip:perf/core] " tip-bot for Jiri Olsa
2019-05-12 15:55 ` [PATCH 2/9] perf: Add attr_groups_update into struct pmu Jiri Olsa
2019-06-03 13:26 ` [tip:perf/core] perf/core: " tip-bot for Jiri Olsa
2019-05-12 15:55 ` [PATCH 3/9] perf/x86: Get rid of x86_pmu::event_attrs Jiri Olsa
2019-06-03 13:26 ` [tip:perf/core] " tip-bot for Jiri Olsa
2019-05-12 15:55 ` [PATCH 4/9] perf/x86: Use the new pmu::update_attrs attribute group Jiri Olsa
2019-06-03 13:27 ` tip-bot for Jiri Olsa [this message]
2019-05-12 15:55 ` [PATCH 5/9] perf/x86: Add is_visible attribute_group callback for base events Jiri Olsa
2019-06-03 13:28 ` [tip:perf/core] " tip-bot for Jiri Olsa
2019-05-12 15:55 ` [PATCH 6/9] perf/x86: Use update attribute groups for caps Jiri Olsa
2019-06-03 13:28 ` [tip:perf/core] " tip-bot for Jiri Olsa
2019-05-12 15:55 ` [PATCH 7/9] perf/x86: Use update attribute groups for extra format Jiri Olsa
2019-06-03 13:29 ` [tip:perf/core] " tip-bot for Jiri Olsa
2019-05-12 15:55 ` [PATCH 8/9] perf/x86/intel: Use update attributes for skylake format Jiri Olsa
2019-06-03 13:30 ` [tip:perf/core] " tip-bot for Jiri Olsa
2019-05-12 15:55 ` [PATCH 9/9] perf/x86: Use update attribute groups for default attributes Jiri Olsa
2019-05-13 9:35 ` Peter Zijlstra
2019-05-13 10:13 ` Jiri Olsa
2019-05-24 13:21 ` [PATCH] perf/x86/intel: Use is_visible callback for default group Jiri Olsa
2019-06-14 10:20 ` Jiri Olsa
2019-06-14 12:34 ` Peter Zijlstra
2019-06-17 14:40 ` [tip:perf/core] perf/x86/intel: Use ->is_visible " tip-bot for Jiri Olsa
2019-06-03 13:31 ` [tip:perf/core] perf/x86: Use update attribute groups for default attributes tip-bot for Jiri Olsa
2019-05-13 9:38 ` [PATCHv2 0/9] perf/x86: Add update attribute groups Peter Zijlstra
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=tip-baa0c83363c7aafb04734acf4ac252be8e13bd88@git.kernel.org \
--to=tipbot@zytor.com \
--cc=acme@kernel.org \
--cc=alexander.shishkin@linux.intel.com \
--cc=gregkh@linuxfoundation.org \
--cc=hpa@zytor.com \
--cc=jolsa@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tip-commits@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=tglx@linutronix.de \
--cc=torvalds@linux-foundation.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox