From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762039AbdDSKLp (ORCPT ); Wed, 19 Apr 2017 06:11:45 -0400 Received: from terminus.zytor.com ([65.50.211.136]:52487 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761924AbdDSKLj (ORCPT ); Wed, 19 Apr 2017 06:11:39 -0400 Date: Wed, 19 Apr 2017 03:10:25 -0700 From: tip-bot for Borislav Petkov Message-ID: Cc: tglx@linutronix.de, bp@suse.de, tony.luck@intel.com, yazen.ghannam@amd.com, hpa@zytor.com, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, mingo@kernel.org Reply-To: mingo@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, hpa@zytor.com, yazen.ghannam@amd.com, bp@suse.de, tony.luck@intel.com, tglx@linutronix.de In-Reply-To: <20170418183924.6agjkebilwqj26or@pd.tnic> References: <20170418183924.6agjkebilwqj26or@pd.tnic> To: linux-tip-commits@vger.kernel.org Subject: [tip:ras/core] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only Git-Commit-ID: c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43 Gitweb: http://git.kernel.org/tip/c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43 Author: Borislav Petkov AuthorDate: Tue, 18 Apr 2017 20:39:24 +0200 Committer: Thomas Gleixner CommitDate: Wed, 19 Apr 2017 12:04:46 +0200 x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only mce_usable_address() does a bunch of basic sanity checks to verify whether the address reported with the error is usable for further processing. However, we do check MCi_STATUS[MISCV] and that is not needed on AMD as that bit says that there's additional information about the logged error in the MCi_MISCj banks. But we don't need that to know whether the address is usable - we only need to know whether the physical address is valid - i.e., ADDRV. On Intel the MISCV bit is needed to perform additional checks to determine whether the reported address is a physical one, etc. Signed-off-by: Borislav Petkov Cc: Yazen Ghannam Cc: Tony Luck Cc: linux-edac Link: http://lkml.kernel.org/r/20170418183924.6agjkebilwqj26or@pd.tnic Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/mcheck/mce.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 9d41ec8..4a29f74 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -491,17 +491,22 @@ static void mce_report_event(struct pt_regs *regs) */ static int mce_usable_address(struct mce *m) { - if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) + if (!(m->status & MCI_STATUS_ADDRV)) return 0; /* Checks after this one are Intel-specific: */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return 1; + if (!(m->status & MCI_STATUS_MISCV)) + return 0; + if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) return 0; + if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) return 0; + return 1; }